第四讲 DSP外设应用之系统时钟Word文件下载.docx

1、Uint16 div3 / Sysclk3 Divider, Valid values are 0, 1 and 3 /corresponding to divide by 1, 2 and 4 respectivelyUint16 oscdiv / CLKOUT3（DSP core clock） divider,Valid values are 0 /（divide by 1） to 31 （divide by 32）程序中，对于MODE,则5502有两种模式：PLL旁路模式和PLL使能模式，前者是时钟未经PLL进行倍频，而后者使用PLL功能。由于目前无源晶振生产工艺限制，其所能产生的频率超

2、过30即会有较大的误差，而5502最高可达到300M时钟，一般需要使能PLL功能。其它参数均为各除法器的值，查询相应的寄存器即可完成。表1 所涉及的PLL寄存器及其各相关位PLLCSR PLLEN, PLLPWRDN, OSCPWRDN, PLLRST, LOCK, STABLEPLLM PLLMPLLDIV0 PLLDIV0, D0ENPLLDIV1 PLLDIV1, D1ENPLLDIV2 PLLDIV2, D2ENPLLDIV3 PLLDIV3, D3ENOSCDIV1 OSCDIV1, OD1ENWAKEUP WKEN0, WKEN1, WKEN2, WKEN3CLKMD CLKMD0

3、CLKOUTSRCLKOUTDIS, CLKOSEL图1 系统时钟发生器图2 晶振及其时钟产生电路图3 内部时钟频率范围值附各个寄存器相关位说明（1） PLL Control / Status Register （PLLCSR） （0x1c80）nSTABLE6R1Oscillator output stable. This bit indicates if the OSCOUT output has stabilized. STABLE = 0: Oscillator output is not yet stable. Oscillator counter is not done count

4、ing 41,032 reference clock cycles.STABLE = 1: Oscillator output is stable. This is true if any one of the three cases is true:a） Oscillator counter has finished counting.b） Oscillator counter is disabled.c） Test mode.LOCK5Lock mode indicator. This bit indicates whether the clock generator is in its

5、lock mode.LOCK = 0: The PLL is in the process of getting a phase lock.LOCK = 1: The clock generator is in the lock mode. The PLL has a phase lock and the output clock of the PLL has the frequency determined by the PLLM register and PLLDIV0 register.PLLRST3R/WAsserts RESET to PLLPLLRST = 0: PLL reset

6、 releasedPLLRST = 1: PLL reset assertedOSCPWRDN2Sets internal oscillator to power-down modeOSCPWRDN = 0: Oscillator operationalOSCPWRDN = 1: Oscillator set to power-down mode based onstate of CLKMD0 bit of Clock Mode Control Register （CLKMD）.When CLKMD0 = 0, the internal oscillator is set to power-d

7、own mode when the clock generator is set to its idle mode CLKIS bit of the IDLE Status Register （ISTR） becomes 1.When CLKMD0 = 1, the internal oscillator is set to power-down mode immediately after the OSCPWRDN bit is set to 1.PLLPWRDNSelects PLL power downPLLPWRDN = 0: PLL operational PLLPWRDN = 1:

8、 PLL placed in power-down statePLLENPLL mode enable. This bit controls the multiplexer before dividers D1, D2, and D3.PLLEN = 0: Bypass mode. Divider D1 and PLL are bypassed. SYSCLK1 to 3 divided downdirectly from input reference clock. PLLEN = 1: PLL mode. Divider D1 and PLL are not bypassed. SYSCL

9、K1 to 3 divided down from PLL output.（2） PLL Multiplier Control Register （PLLM）15-54-0Reserved4:00000PLL multiplier-selectPLLM = 0000000001: ReservedPLLM = 00010: Times 2PLLM = 00011: Times 3PLLM = 00100: Times 4PLLM = 00101: Times 5PLLM = 00110: Times 6PLLM = 00111: Times 7PLLM = 01000: Times 8PLLM

10、 = 01001: Times 9PLLM = 01010: Times 10PLLM = 01011: Times 11PLLM = 01100: Times 12PLLM = 01101: Times 13PLLM = 01110: Times 14PLLM = 01111: Times 15PLLM = 1000011111:（3） PLL Divider 0 Register （PLLDIV0） （Prescaler）1514-5D0ENPLLDIV0Divider D0 enableD0EN = 0: Divider 0 disabledD0EN = 1: Divider 0 ena

11、bledDivider D0 ratioPLLDIV0 = 00000: Divide by 1PLLDIV0 = 00001: Divide by 2PLLDIV0 = 00010: Divide by 3.PLLDIV0 = 11111: Divide by 32（4）PLL Divider1 Register （PLLDIV1） for SYSCLK1D1ENPLLDIV1Divider D1 enableD1EN = 0: Divider 1 disabledD1EN = 1: Divider 1 enabled00011Divider D1 ratio （SYSCLK1 divider）PLLDIV1 = 00000:PLLDIV1 = 00001:PLLDIV1 = 00010: ReservedPLLDIV1 = 00011: Divide by 4PLLDIV1 = 0010011111:PLLDIV2和PLLDIV3的位定义与PLLDIV1完全一样，在此不再重复写了。（5） Oscillator Divider1 Register （OSCDIV