第四讲 DSP外设应用之系统时钟Word文件下载.docx
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Uint16div3//Sysclk3Divider,Validvaluesare0,1and3
//correspondingtodivideby1,2and4respectively
Uint16oscdiv//CLKOUT3（DSPcoreclock）divider,Validvaluesare0
//（divideby1）to31（divideby32）
程序中，对于MODE,则5502有两种模式：
PLL旁路模式和PLL使能模式，前者是时钟未经PLL进行倍频，而后者使用PLL功能。
由于目前无源晶振生产工艺限制，其所能产生的频率超过30即会有较大的误差，而5502最高可达到300M时钟，一般需要使能PLL功能。
其它参数均为各除法器的值，查询相应的寄存器即可完成。
表1所涉及的PLL寄存器及其各相关位
PLLCSR
PLLEN,PLLPWRDN,OSCPWRDN,PLLRST,LOCK,STABLE
PLLM
PLLM
PLLDIV0
PLLDIV0,D0EN
PLLDIV1
PLLDIV1,D1EN
PLLDIV2
PLLDIV2,D2EN
PLLDIV3
PLLDIV3,D3EN
OSCDIV1
OSCDIV1,OD1EN
WAKEUP
WKEN0,WKEN1,WKEN2,WKEN3
CLKMD
CLKMD0
CLKOUTSR
CLKOUTDIS,CLKOSEL
图1系统时钟发生器
图2晶振及其时钟产生电路
图3内部时钟频率范围值
附各个寄存器相关位说明
（1）PLLControl/StatusRegister（PLLCSR）（0x1c80）
n
STABLE
6
R
1
Oscillatoroutputstable.ThisbitindicatesiftheOSCOUToutputhasstabilized.
STABLE=0:
Oscillatoroutputisnotyetstable.
Oscillatorcounterisnotdonecounting41,032referenceclockcycles.
STABLE=1:
Oscillatoroutputisstable.Thisistrueifanyoneofthethreecasesistrue:
a）Oscillatorcounterhasfinishedcounting.
b）Oscillatorcounterisdisabled.
c）Testmode.
LOCK
5
Lockmodeindicator.Thisbitindicateswhethertheclockgeneratorisinitslockmode.
LOCK=0:
ThePLLisintheprocessofgettingaphaselock.
LOCK=1:
Theclockgeneratorisinthelockmode.ThePLLhasaphaselockandtheoutputclockofthePLLhasthefrequencydeterminedbythePLLMregisterandPLLDIV0register.
PLLRST
3
R/W
AssertsRESETtoPLL
PLLRST=0:
PLLresetreleased
PLLRST=1:
PLLresetasserted
OSCPWRDN
2
Setsinternaloscillatortopower-downmode
OSCPWRDN=0:
Oscillatoroperational
OSCPWRDN=1:
Oscillatorsettopower-downmodebasedonstateofCLKMD0bitofClockModeControlRegister（CLKMD）.
WhenCLKMD0=0,theinternaloscillatorissettopower-downmodewhentheclockgeneratorissettoitsidlemode[CLKISbitoftheIDLEStatusRegister（ISTR）becomes1].
WhenCLKMD0=1,theinternaloscillatorissettopower-downmodeimmediatelyaftertheOSCPWRDNbitissetto1.
PLLPWRDN
SelectsPLLpowerdown
PLLPWRDN=0:
PLLoperational
PLLPWRDN=1:
PLLplacedinpower-downstate
PLLEN
PLLmodeenable.ThisbitcontrolsthemultiplexerbeforedividersD1,D2,andD3.
PLLEN=0:
Bypassmode.DividerD1andPLLarebypassed.SYSCLK1to3divideddown
directlyfrominputreferenceclock.
PLLEN=1:
PLLmode.DividerD1andPLLarenotbypassed.SYSCLK1to3divideddownfromPLLoutput.
（2）PLLMultiplierControlRegister（PLLM）
15-5
4-0
Reserved
4:
00000
PLLmultiplier-select
PLLM=00000−00001:
Reserved
PLLM=00010:
Times2
PLLM=00011:
Times3
PLLM=00100:
Times4
PLLM=00101:
Times5
PLLM=00110:
Times6
PLLM=00111:
Times7
PLLM=01000:
Times8
PLLM=01001:
Times9
PLLM=01010:
Times10
PLLM=01011:
Times11
PLLM=01100:
Times12
PLLM=01101:
Times13
PLLM=01110:
Times14
PLLM=01111:
Times15
PLLM=10000−11111:
（3）PLLDivider0Register（PLLDIV0）（Prescaler）
15
14-5
D0EN
PLLDIV0
DividerD0enable
D0EN=0:
Divider0disabled
D0EN=1:
Divider0enabled
DividerD0ratio
PLLDIV0=00000:
Divideby1
PLLDIV0=00001:
Divideby2
PLLDIV0=00010:
Divideby3
.
PLLDIV0=11111:
Divideby32
（4）PLLDivider1Register（PLLDIV1）forSYSCLK1
D1EN
PLLDIV1
DividerD1enable
D1EN=0:
Divider1disabled
D1EN=1:
Divider1enabled
00011
DividerD1ratio（SYSCLK1divider）
PLLDIV1=00000:
PLLDIV1=00001:
PLLDIV1=00010:
Reserved
PLLDIV1=00011:
Divideby4
PLLDIV1=00100−11111:
PLLDIV2和PLLDIV3的位定义与PLLDIV1完全一样，在此不再重复写了。
（5）OscillatorDivider1Register（OSCDIV
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