FIFO Verilog文档格式.docx

1、 F_FirstN, F_EmptyN ）;input Clk; / CLK signal.input RstN; / Low Asserted Reset signal.input （FWIDTH-1）:0 Data_In; / Data into FIFO.input FInN; / Write into FIFO Signal.input FClrN; / Clear signal to FIFO.input FOutN; / Read from FIFO signal.output （FWIDTH-1）:0 F_Data; / FIFO data out.output F_FullN;

2、 / FIFO full indicating signal.output F_EmptyN; / FIFO empty indicating signal.output F_LastN; / FIFO Last but one signal.output F_SLastN; / FIFO SLast but one signal.output F_FirstN; / Signal indicating only one / word in FIFO.reg F_FullN;reg F_EmptyN;reg F_LastN;reg F_SLastN;reg F_FirstN;reg FCWID

3、TH:0 fcounter; /counter indicates num of data in FIFOreg （FCWIDTH-1）:0 rd_ptr; / Current read pointer.0 wr_ptr; / Current write pointer.wire （FWIDTH-1）:0 FIFODataOut; / Data out from FIFO MemBlk0 FIFODataIn; / Data into FIFO MemBlkwire ReadN = FOutN;wire WriteN = FInN;assign F_Data = FIFODataOut;ass

4、ign FIFODataIn = Data_In; FIFO_MEM_BLK memblk（.clk（Clk）, .writeN（WriteN）, .rd_addr（rd_ptr）, .wr_addr（wr_ptr）, .data_in（FIFODataIn）, .data_out（FIFODataOut） / Control circuitry for FIFO. If reset or clr signal is asserted, / all the counters are set to 0. If write only the write counter / is increment

5、ed else if read only read counter is incremented / else if both, read and write counters are incremented. / fcounter indicates the num of items in the FIFO. Write only / increments the fcounter, read only decrements the counter, and / read & write doesnt change the counter value. always （posedge Clk

6、 or negedge RstN） begin if（!RstN） begin fcounter = 0; rd_ptr wr_ptr end else beginFClrN ） beginWriteN & F_FullN）= wr_ptr + 1;ReadN & F_EmptyN）= rd_ptr + 1; ReadN &= fcounter + 1; else if（WriteN & != fcounter - 1; / All the FIFO status signals depends on the value of fcounter. / If the fcounter is eq

7、ual to fdepth, indicates FIFO is full. / If the fcounter is equal to zero, indicates the FIFO is empty. / F_EmptyN signal indicates FIFO Empty Status. By default it is / asserted, indicating the FIFO is empty. After the First Data is / put into the FIFO the signal is deasserted.RstN） F_EmptyN = 1b0;

8、 if（FClrN=1b1） begin if（F_EmptyN=1b0 & WriteN=1b0）b1; else if（F_FirstN=1 ReadN=1b1） else / F_FirstN signal indicates that there is only one datum sitting / in the FIFO. When the FIFO is empty and a write to FIFO occurs, / this signal gets asserted. F_FirstN if（F_EmptyN=1b0） | （fcounter=2 &b1） else i

9、f （F_FirstN=1 （WriteN ReadN） / F_SLastN indicates that there is space for only two data words /in the FIFO. F_SLastN if（ （F_LastN=1b1） | （fcounter = （FDEPTH-3） & else if（F_SLastN=1 （ReadN WriteN） ） / F_LastN indicates that there is one space for only one data / word in the FIFO. F_LastN if （F_FullN=1 （fcounter = （FDEPTH-2） & else if（F_LastN=1 / F_FullN indicates that the FIFO is full. F_FullN if （F_LastN=1 else if（F_FullN=1endmodule/ Configurable memory block for fifo. The width of the mem/ block is configu