自动化专业毕业设计翻译正文.docx

1、自动化专业毕业设计翻译正文Universal Serial Communication Interface SPI ModeThe universal serial communication interface (USCI) supports multiple serial communication modes withone hardware module. This chapter discusses the operation of the synchronous peripheral interface (SPI)16.1 mode.Universal Serial Communi

2、cation Interface (USCI) OverviewThe universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. Each different USCI module is named with a different letter. For example, USCI_A is different from USCI_B, etc. If

3、more than one identical USCI module is implemented on one device, those modules are named with incrementing numbers. For example, if one device has two USCI_A modules, they are named USCI_A0 and USCI_A1. See the device-specific data sheet to determine which USCI modules, if any, are implemented on w

4、hich devices.USCI_Ax modules support: UART mode Pulse shaping for IrDA communications Automatic baud-rate detection for LIN communications SPI modeUSCI_Bx modules support: mode SPI mode16.2 USCI Introduction SPI ModeIn synchronous mode, the USCI connects the device to an external system via three or

5、 four pins:UCxSIMO, UCxSOMI, UCxCLK, and UCxSTE. SPI mode is selected when the UCSYNC bit is set, and SPI mode (3-pin or 4-pin) is selected with the UCMODEx bits.SPI mode features include: 7-bit or 8-bit data length LSB-first or MSB-first data transmit and receive 3-pin and 4-pin SPI operation Maste

6、r or slave modes Independent transmit and receive shift registers Separate transmit and receive buffer registers Continuous transmit and receive operation Selectable clock polarity and phase control Programmable clock frequency in master mode Independent interrupt capability for receive and transmit

7、 Slave operation in LPM4Figure16-1 shows the USCI when configured for SPI mode.16.3 USCI Operation SPI ModeIn SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, UCxSTE, is provided to enable a device to receive and tr

8、ansmit data and is controlled by the master.Three or four signals are used for SPI data exchange: UCxSIMO slave in, master out Master mode: UCxSIMO is the data output line. Slave mode: UCxSIMO is the data input line. UCxSOMI slave out, master in Master mode: UCxSOMI is the data input line. Slave mod

9、e: UCxSOMI is the data output line. UCxCLK USCI SPI clock Master mode: UCxCLK is an output. Slave mode: UCxCLK is an input. UCxSTE slave transmit enable. Used in 4-pin mode to allow multiple masters on a single bus. Not used in 3-pin mode. Table 16-1 describes the UCxSTE operation.16.3.1 USCI Initia

10、lization and ResetThe USCI is reset by a PUC or by the UCSWRST bit. After a PUC, the UCSWRST bit is automatically set,keeping the USCI in a reset condition. When set, the UCSWRST bit resets the UCRXIE, UCTXIE,UCRXIFG, UCOE, and UCFE bits, and sets the UCTXIFG flag. Clearing UCSWRST releases the USCI

11、 for operation.Note: Initializing or reconfiguring the USCI moduleThe recommended USCI initialization/reconfiguration process is:1. Set UCSWRST ( BIS.B #UCSWRST, & UCxCTL1 ).2. Initialize all USCI registers with UCSWRST = 1 (including UCxCTL1).3. Configure ports.4. Clear UCSWRST via software ( BIC.B

12、 #UCSWRST, & UCxCTL1 ).5. Enable interrupts (optional) via UCRXIE and/or UCTXIE.16.3.2 Character FormatThe USCI module in SPI mode supports 7-bit and 8-bit character lengths selected by the UC7BIT bit. In 7-bit data mode, UCxRXBUF is LSB justified and the MSB is always reset. The UCMSB bit controls

13、the direction of the transfer and selects LSB or MSB first.Note: Default character formatThe default SPI character transmission is LSB first. For communication with other SPI interfaces, MSB-first mode may be required.Note: Character format for FiguresFigures throughout this chapter use MSB-first fo

14、rmat.16.3.3 Master ModeFigure 16-2 shows the USCI as a master in both 3-pin and 4-pin configurations. The USCI initiates data transfer when data is moved to the transmit data buffer UCxTXBUF. The UCxTXBUF data is moved to the transmit (TX) shift register when the TX shift register is empty, initiati

15、ng data transfer on UCxSIMO starting with either the MSB or LSB, depending on the UCMSB setting. Data on UCxSOMI is shifted into the receive shift register on the opposite clock edge. When the character is received, the receive data is moved from the receive (RX) shift register to the received data

16、buffer UCxRXBUF and the receive interrupt flag UCRXIFG is set, indicating the RX/TX operation is complete.A set transmit interrupt flag, UCTXIFG, indicates that data has moved from UCxTXBUF to the TX shift register and UCxTXBUF is ready for new data. It does not indicate RX/TX completion.To receive

17、data into the USCI in master mode, data must be written to UCxTXBUF, because receive and transmit operations operate concurrently.16.3.4 Slave ModeFigure 16-3 shows the USCI as a slave in both 3-pin and 4-pin configurations. UCxCLK is used as the input for the SPI clock and must be supplied by the e

18、xternal master. The data-transfer rate is determined by this clock and not by the internal bit clock generator. Data written to UCxTXBUF and moved to the TX shift register before the start of UCxCLK is transmitted on UCxSOMI. Data on UCxSIMO is shifted into the receive shift register on the opposite

19、 edge of UCxCLK and moved to UCxRXBUF when the set number of bits are received. When data is moved from the RX shift register to UCxRXBUF, the UCRXIFG interrupt flag is set, indicating that data has been received. The overrun error bit UCOE is set when the previously received data is not read from U

20、CxRXBUF before new data is moved to UCxRXBUF.16.3.5 SPI EnableWhen the USCI module is enabled by clearing the UCSWRST bit, it is ready to receive and transmit. In master mode, the bit clock generator is ready, but is not clocked nor producing any clocks. In slave mode, the bit clock generator is dis

21、abled and the clock is provided by the master.A transmit or receive operation is indicated by UCBUSY = 1.A PUC or set UCSWRST bit disables the USCI immediately and any active transfer is terminated.Transmit EnableIn master mode, writing to UCxTXBUF activates the bit clock generator, and the data beg

22、ins to transmit.In slave mode, transmission begins when a master provides a clock and, in 4-pin mode, when the UCxSTE is in the slave-active state.Receive EnableThe SPI receives data when a transmission is active. Receive and transmit operations operate concurrently. 16.3.6 Serial Clock ControlUCxCL

23、K is provided by the master on the SPI bus. When UCMST = 1, the bit clock is provided by the USCI bit clock generator on the UCxCLK pin. The clock used to generate the bit clock is selected with the UCSSELx bits. When UCMST = 0, the USCI clock is provided on the UCxCLK pin by the master, the bit clo

24、ck generator is not used, and the UCSSELx bits are dont care. The SPI receiver and transmitter operate in parallel and use the same clock source for data transfer.The 16-bit value of UCBRx in the bit rate control registers (UCxxBR1 and UCxxBR0) is the division factor of the USCI clock source, BRCLK.

25、 The maximum bit clock that can be generated in master mode is BRCLK. Modulation is not used in SPI mode, and UCAxMCTL should be cleared when using SPI mode for USCI_A. The UCAxCLK/UCBxCLK frequency is given by: = /UCBRxSerial Clock Polarity and PhaseThe polarity and phase of UCxCLK are independentl

26、y configured via the UCCKPL and UCCKPH control bits of the USCI. Timing for each case is shown in Figure 16-4 . 16.3.7 Using the SPI Mode With Low-Power ModesThe USCI module provides automatic clock activation for use with low-power modes. When the USCI clock source is inactive because the device is

27、 in a low-power mode, the USCI module automatically activates it when needed, regardless of the control-bit settings for the clock source. The clock remains active until the USCI module returns to its idle condition. After the USCI module returns to the idle condition, control of the clock source re

28、verts to the settings of its control bits.In SPI slave mode, no internal clock source is required because the clock is provided by the external master. It is possible to operate the USCI in SPI slave mode while the device is in LPM4 and all clock sources are disabled. The receive or transmit interru

29、pt can wake up the CPU from any low-power mode. 16.3.8 SPI InterruptsThe USCI has only one interrupt vector that is shared for transmission and for reception. USCI_Ax and USC_Bx do not share the same interrupt vector.SPI Transmit Interrupt OperationThe UCTXIFG interrupt flag is set by the transmitte

30、r to indicate that UCxTXBUF is ready to accept another character. An interrupt request is generated if UCTXIE and GIE are also set. UCTXIFG is automatically reset if a character is written to UCxTXBUF. UCTXIFG is set after a PUC or when UCSWRST = 1. UCTXIE is reset after a PUC or when UCSWRST = 1.No

31、te: Writing to UCxTXBUF in SPI modeData written to UCxTXBUF when UCTXIFG = 0 may result in erroneous data transmission.SPI Receive Interrupt OperationThe UCRXIFG interrupt flag is set each time a character is received and loaded into UCxRXBUF. An interrupt request is generated if UCRXIE and GIE are

32、also set. UCRXIFG and UCRXIE are reset by a system reset PUC signal or when UCSWRST = 1. UCRXIFG is automatically reset when UCxRXBUF is read. UCxIV, Interrupt Vector GeneratorThe USCI interrupt flags are prioritized and combined to source a single interrupt vector. The interrupt vector register UCxIV is used to determine which flag requested an interrupt. The highest-priority enabled interrupt generates a number in the UCxIV register that can be evaluated or added to the program counter