MSP430SFR.docx

1、MSP430SFR* MSP430G2231 devices.*/#ifndef _MSP430G2231#define _MSP430G2231#ifdef _cplusplusextern C #endif/*-*/* PERIPHERAL FILE MAP */*-*/* External references resolved by a device-specific linker command file */#define SFR_8BIT(address) extern volatile unsigned char address#define SFR_16BIT(address

2、) extern volatile unsigned int address/* STANDARD BITS*/#define BIT0 (0x0001)#define BIT1 (0x0002)#define BIT2 (0x0004)#define BIT3 (0x0008)#define BIT4 (0x0010)#define BIT5 (0x0020)#define BIT6 (0x0040)#define BIT7 (0x0080)#define BIT8 (0x0100)#define BIT9 (0x0200)#define BITA (0x0400)#define BITB

3、(0x0800)#define BITC (0x1000)#define BITD (0x2000)#define BITE (0x4000)#define BITF (0x8000)/* STATUS REGISTER BITS*/#define C (0x0001)#define Z (0x0002)#define N (0x0004)#define V (0x0100)#define GIE (0x0008) /*中断控制位 */#define CPUOFF (0x0010)#define OSCOFF (0x0020)#define SCG0 (0x0040)#define SCG1

4、(0x0080)/* Low Power Modes coded with Bits 4-7 in SR */#ifdef _ASM_HEADER_ /* Begin #defines for assembler */#define LPM0 (CPUOFF)#define LPM1 (SCG0+CPUOFF)#define LPM2 (SCG1+CPUOFF)#define LPM3 (SCG1+SCG0+CPUOFF)#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)/* End #defines for assembler */#else /* Begin #d

5、efines for C */#define LPM0_bits (CPUOFF)#define LPM1_bits (SCG0+CPUOFF)#define LPM2_bits (SCG1+CPUOFF)#define LPM3_bits (SCG1+SCG0+CPUOFF)#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)#include in430.h#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */#define LPM0_EXIT _bic_SR_registe

6、r_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */#define LPM2_EXIT _bic_SR_registe

7、r_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */#define LPM4_EXIT _bic_SR_registe

8、r_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */#endif /* End #defines for C */* PERIPHERAL FILE MAP*/* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS*/SFR_8BIT(IE1); /* Interrupt Enable 1 */#define WDTIE (0x01) /* Watchdog Interrupt Enable */#define OFIE (0x02) /* Osc. Fault Interrupt Enable */

9、#define NMIIE (0x10) /* NMI Interrupt Enable */#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */SFR_8BIT(IFG1); /* Interrupt Flag 1 */#define WDTIFG (0x01) /* Watchdog Interrupt Flag */#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */#define PORIFG (0x04) /* Power On Interrupt F

10、lag */#define RSTIFG (0x08) /* Reset Interrupt Flag */#define NMIIFG (0x10) /* NMI Interrupt Flag */* ADC10*/#define _MSP430_HAS_ADC10_ /* Definition to show that Module is available */SFR_8BIT(ADC10DTC0); /* ADC10 Data Transfer Control 0 */SFR_8BIT(ADC10DTC1); /* ADC10 Data Transfer Control 1 */SFR

11、_8BIT(ADC10AE0); /* ADC10 Analog Enable 0 */SFR_16BIT(ADC10CTL0); /* ADC10 Control 0 */SFR_16BIT(ADC10CTL1); /* ADC10 Control 1 */SFR_16BIT(ADC10MEM); /* ADC10 Memory */SFR_16BIT(ADC10SA); /* ADC10 Data Transfer Start Address */* ADC10CTL0 */#define ADC10SC (0x001) /* ADC10 Start Conversion */#defin

12、e ENC (0x002) /* ADC10 Enable Conversion */#define ADC10IFG (0x004) /* ADC10 Interrupt Flag */#define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */#define ADC10ON (0x010) /* ADC10 On/Enable */#define REFON (0x020) /* ADC10 Reference on */#define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */#define

13、MSC (0x080) /* ADC10 Multiple SampleConversion */#define REFBURST (0x100) /* ADC10 Reference Burst Mode */#define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */#define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */#define ADC10SHT0 (0x800) /* ADC10 Sample Hold Select Bit: 0 */#defi

14、ne ADC10SHT1 (0x1000) /* ADC10 Sample Hold Select Bit: 1 */#define SREF0 (0x2000) /* ADC10 Reference Select Bit: 0 */#define SREF1 (0x4000) /* ADC10 Reference Select Bit: 1 */#define SREF2 (0x8000) /* ADC10 Reference Select Bit: 2 */#define ADC10SHT_0 (0*0x800u) /* 4 x ADC10CLKs */#define ADC10SHT_1

15、 (1*0x800u) /* 8 x ADC10CLKs */#define ADC10SHT_2 (2*0x800u) /* 16 x ADC10CLKs */#define ADC10SHT_3 (3*0x800u) /* 64 x ADC10CLKs */#define SREF_0 (0*0x2000u) /* VR+ = AVCC and VR- = AVSS */#define SREF_1 (1*0x2000u) /* VR+ = VREF+ and VR- = AVSS */#define SREF_2 (2*0x2000u) /* VR+ = VEREF+ and VR- =

16、 AVSS */#define SREF_3 (3*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */#define SREF_4 (4*0x2000u) /* VR+ = AVCC and VR- = VREF-/VEREF- */#define SREF_5 (5*0x2000u) /* VR+ = VREF+ and VR- = VREF-/VEREF- */#define SREF_6 (6*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- #define SREF_7 (7*0x2000u) /* VR+

17、 = VEREF+ and VR- = VREF-/VEREF- /* ADC10CTL1 */#define ADC10BUSY (0x0001) /* ADC10 BUSY */#define CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 #define CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 #define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select Bit: 0 */#define ADC10SSEL

18、1 (0x0010) /* ADC10 Clock Source Select Bit: 1 */#define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select Bit: 0 */#define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select Bit: 1 */#define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select Bit: 2 */#define ISSH (0x0100) /* ADC10 Invert Sample Hold Sig

19、nal */#define ADC10DF (0x0200) /* ADC10 Data Format 0:binary 1:2s complement */#define SHS0 (0x0400) /* ADC10 Sample/Hold Source Bit: 0 */#define SHS1 (0x0800) /* ADC10 Sample/Hold Source Bit: 1 */#define INCH0 (0x1000) /* ADC10 Input Channel Select Bit: 0 */#define INCH1 (0x2000) /* ADC10 Input Cha

20、nnel Select Bit: 1 */#define INCH2 (0x4000) /* ADC10 Input Channel Select Bit: 2 */#define INCH3 (0x8000) /* ADC10 Input Channel Select Bit: 3 */#define CONSEQ_0 (0*2u) /* Single channel single conversion */#define CONSEQ_1 (1*2u) /* Sequence of channels */#define CONSEQ_2 (2*2u) /* Repeat single ch

21、annel */#define CONSEQ_3 (3*2u) /* Repeat sequence of channels */#define ADC10SSEL_0 (0*8u) /* ADC10OSC */#define ADC10SSEL_1 (1*8u) /* ACLK */#define ADC10SSEL_2 (2*8u) /* MCLK */#define ADC10SSEL_3 (3*8u) /* SMCLK */#define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select 0 */#define ADC10DIV_1

22、(1*0x20u) /* ADC10 Clock Divider Select 1 */#define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select 2 */#define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select 3 */#define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select 4 */#define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select 5 */#def

23、ine ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select 6 */#define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select 7 */#define SHS_0 (0*0x400u) /* ADC10SC */#define SHS_1 (1*0x400u) /* TA3 OUT1 */#define SHS_2 (2*0x400u) /* TA3 OUT0 */#define SHS_3 (3*0x400u) /* TA3 OUT2 */#define INCH_0 (0*0x100

24、0u) /* Selects Channel 0 */#define INCH_1 (1*0x1000u) /* Selects Channel 1 */#define INCH_2 (2*0x1000u) /* Selects Channel 2 */#define INCH_3 (3*0x1000u) /* Selects Channel 3 */#define INCH_4 (4*0x1000u) /* Selects Channel 4 */#define INCH_5 (5*0x1000u) /* Selects Channel 5 */#define INCH_6 (6*0x100

25、0u) /* Selects Channel 6 */#define INCH_7 (7*0x1000u) /* Selects Channel 7 */#define INCH_8 (8*0x1000u) /* Selects Channel 8 */#define INCH_9 (9*0x1000u) /* Selects Channel 9 */#define INCH_10 (10*0x1000u) /* Selects Channel 10 */#define INCH_11 (11*0x1000u) /* Selects Channel 11 */#define INCH_12 (

26、12*0x1000u) /* Selects Channel 12 */#define INCH_13 (13*0x1000u) /* Selects Channel 13 */#define INCH_14 (14*0x1000u) /* Selects Channel 14 */#define INCH_15 (15*0x1000u) /* Selects Channel 15 */* ADC10DTC0 */#define ADC10FETCH (0x001) /* This bit should normally be reset */#define ADC10B1 (0x002) /

27、* ADC10 block one */#define ADC10CT (0x004) /* ADC10 continuous transfer */#define ADC10TB (0x008) /* ADC10 two-block mode */#define ADC10DISABLE (0x000) /* ADC10DTC1 */* Basic Clock Module*/#define _MSP430_HAS_BC2_ /* Definition to show that Module is available */SFR_8BIT(DCOCTL); /* DCO Clock Freq

28、uency Control */SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */SFR_8BIT(BCSCTL3); /* Basic Clock System Control 3 */#define MOD0 (0x01) /* Modulation Bit 0 */#define MOD1 (0x02) /* Modulation Bit 1 */#define MOD2 (0x04) /* Modulation Bit 2 */#define MOD3 (0x08) /* Modulation Bit 3 */#define MOD4 (0x10) /* Modulation Bit 4 */#define DCO0 (0x20) /* DCO Select Bit 0 */#define DCO1 (0x40) /* DCO Select Bit 1 */#define DCO2 (0x80) /* DCO Select Bit 2 */#define RSEL0 (0x01) /* Range