MSP430SFR.docx
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MSP430SFR
*MSP430G2231devices.
********************************************************************/
#ifndef__MSP430G2231
#define__MSP430G2231
#ifdef__cplusplus
extern"C"{
#endif
/*----------------------------------------------------------------------------*/
/*PERIPHERALFILEMAP*/
/*----------------------------------------------------------------------------*/
/*Externalreferencesresolvedbyadevice-specificlinkercommandfile*/
#defineSFR_8BIT(address)externvolatileunsignedcharaddress
#defineSFR_16BIT(address)externvolatileunsignedintaddress
/************************************************************
*STANDARDBITS
************************************************************/
#defineBIT0(0x0001)
#defineBIT1(0x0002)
#defineBIT2(0x0004)
#defineBIT3(0x0008)
#defineBIT4(0x0010)
#defineBIT5(0x0020)
#defineBIT6(0x0040)
#defineBIT7(0x0080)
#defineBIT8(0x0100)
#defineBIT9(0x0200)
#defineBITA(0x0400)
#defineBITB(0x0800)
#defineBITC(0x1000)
#defineBITD(0x2000)
#defineBITE(0x4000)
#defineBITF(0x8000)
/************************************************************
*STATUSREGISTERBITS
************************************************************/
#defineC(0x0001)
#defineZ(0x0002)
#defineN(0x0004)
#defineV(0x0100)
#defineGIE(0x0008)/*中断控制位*/
#defineCPUOFF(0x0010)
#defineOSCOFF(0x0020)
#defineSCG0(0x0040)
#defineSCG1(0x0080)
/*LowPowerModescodedwithBits4-7inSR*/
#ifdef__ASM_HEADER__/*Begin#definesforassembler*/
#defineLPM0(CPUOFF)
#defineLPM1(SCG0+CPUOFF)
#defineLPM2(SCG1+CPUOFF)
#defineLPM3(SCG1+SCG0+CPUOFF)
#defineLPM4(SCG1+SCG0+OSCOFF+CPUOFF)
/*End#definesforassembler*/
#else/*Begin#definesforC*/
#defineLPM0_bits(CPUOFF)
#defineLPM1_bits(SCG0+CPUOFF)
#defineLPM2_bits(SCG1+CPUOFF)
#defineLPM3_bits(SCG1+SCG0+CPUOFF)
#defineLPM4_bits(SCG1+SCG0+OSCOFF+CPUOFF)
#include"in430.h"
#defineLPM0_bis_SR_register(LPM0_bits)/*EnterLowPowerMode0*/
#defineLPM0_EXIT_bic_SR_register_on_exit(LPM0_bits)/*ExitLowPowerMode0*/
#defineLPM1_bis_SR_register(LPM1_bits)/*EnterLowPowerMode1*/
#defineLPM1_EXIT_bic_SR_register_on_exit(LPM1_bits)/*ExitLowPowerMode1*/
#defineLPM2_bis_SR_register(LPM2_bits)/*EnterLowPowerMode2*/
#defineLPM2_EXIT_bic_SR_register_on_exit(LPM2_bits)/*ExitLowPowerMode2*/
#defineLPM3_bis_SR_register(LPM3_bits)/*EnterLowPowerMode3*/
#defineLPM3_EXIT_bic_SR_register_on_exit(LPM3_bits)/*ExitLowPowerMode3*/
#defineLPM4_bis_SR_register(LPM4_bits)/*EnterLowPowerMode4*/
#defineLPM4_EXIT_bic_SR_register_on_exit(LPM4_bits)/*ExitLowPowerMode4*/
#endif/*End#definesforC*/
/************************************************************
*PERIPHERALFILEMAP
************************************************************/
/************************************************************
*SPECIALFUNCTIONREGISTERADDRESSES+CONTROLBITS
************************************************************/
SFR_8BIT(IE1);/*InterruptEnable1*/
#defineWDTIE(0x01)/*WatchdogInterruptEnable*/
#defineOFIE(0x02)/*Osc.FaultInterruptEnable*/
#defineNMIIE(0x10)/*NMIInterruptEnable*/
#defineACCVIE(0x20)/*FlashAccessViolationInterruptEnable*/
SFR_8BIT(IFG1);/*InterruptFlag1*/
#defineWDTIFG(0x01)/*WatchdogInterruptFlag*/
#defineOFIFG(0x02)/*Osc.FaultInterruptFlag*/
#definePORIFG(0x04)/*PowerOnInterruptFlag*/
#defineRSTIFG(0x08)/*ResetInterruptFlag*/
#defineNMIIFG(0x10)/*NMIInterruptFlag*/
/************************************************************
*ADC10
************************************************************/
#define__MSP430_HAS_ADC10__/*DefinitiontoshowthatModuleisavailable*/
SFR_8BIT(ADC10DTC0);/*ADC10DataTransferControl0*/
SFR_8BIT(ADC10DTC1);/*ADC10DataTransferControl1*/
SFR_8BIT(ADC10AE0);/*ADC10AnalogEnable0*/
SFR_16BIT(ADC10CTL0);/*ADC10Control0*/
SFR_16BIT(ADC10CTL1);/*ADC10Control1*/
SFR_16BIT(ADC10MEM);/*ADC10Memory*/
SFR_16BIT(ADC10SA);/*ADC10DataTransferStartAddress*/
/*ADC10CTL0*/
#defineADC10SC(0x001)/*ADC10StartConversion*/
#defineENC(0x002)/*ADC10EnableConversion*/
#defineADC10IFG(0x004)/*ADC10InterruptFlag*/
#defineADC10IE(0x008)/*ADC10InterruptEnalbe*/
#defineADC10ON(0x010)/*ADC10On/Enable*/
#defineREFON(0x020)/*ADC10Referenceon*/
#defineREF2_5V(0x040)/*ADC10Ref0:
1.5V/1:
2.5V*/
#defineMSC(0x080)/*ADC10MultipleSampleConversion*/
#defineREFBURST(0x100)/*ADC10ReferenceBurstMode*/
#defineREFOUT(0x200)/*ADC10EnalbeoutputofRef.*/
#defineADC10SR(0x400)/*ADC10SamplingRate0:
200ksps/1:
50ksps*/
#defineADC10SHT0(0x800)/*ADC10SampleHoldSelectBit:
0*/
#defineADC10SHT1(0x1000)/*ADC10SampleHoldSelectBit:
1*/
#defineSREF0(0x2000)/*ADC10ReferenceSelectBit:
0*/
#defineSREF1(0x4000)/*ADC10ReferenceSelectBit:
1*/
#defineSREF2(0x8000)/*ADC10ReferenceSelectBit:
2*/
#defineADC10SHT_0(0*0x800u)/*4xADC10CLKs*/
#defineADC10SHT_1(1*0x800u)/*8xADC10CLKs*/
#defineADC10SHT_2(2*0x800u)/*16xADC10CLKs*/
#defineADC10SHT_3(3*0x800u)/*64xADC10CLKs*/
#defineSREF_0(0*0x2000u)/*VR+=AVCCandVR-=AVSS*/
#defineSREF_1(1*0x2000u)/*VR+=VREF+andVR-=AVSS*/
#defineSREF_2(2*0x2000u)/*VR+=VEREF+andVR-=AVSS*/
#defineSREF_3(3*0x2000u)/*VR+=VEREF+andVR-=AVSS*/
#defineSREF_4(4*0x2000u)/*VR+=AVCCandVR-=VREF-/VEREF-*/
#defineSREF_5(5*0x2000u)/*VR+=VREF+andVR-=VREF-/VEREF-*/
#defineSREF_6(6*0x2000u)/*VR+=VEREF+andVR-=VREF-/VEREF-#defineSREF_7(7*0x2000u)/*VR+=VEREF+andVR-=VREF-/VEREF-
/*ADC10CTL1*/
#defineADC10BUSY(0x0001)/*ADC10BUSY*/
#defineCONSEQ0(0x0002)/*ADC10ConversionSequenceSelect0
#defineCONSEQ1(0x0004)/*ADC10ConversionSequenceSelect1
#defineADC10SSEL0(0x0008)/*ADC10ClockSourceSelectBit:
0*/
#defineADC10SSEL1(0x0010)/*ADC10ClockSourceSelectBit:
1*/
#defineADC10DIV0(0x0020)/*ADC10ClockDividerSelectBit:
0*/
#defineADC10DIV1(0x0040)/*ADC10ClockDividerSelectBit:
1*/
#defineADC10DIV2(0x0080)/*ADC10ClockDividerSelectBit:
2*/
#defineISSH(0x0100)/*ADC10InvertSampleHoldSignal*/
#defineADC10DF(0x0200)/*ADC10DataFormat0:
binary1:
2'scomplement*/
#defineSHS0(0x0400)/*ADC10Sample/HoldSourceBit:
0*/
#defineSHS1(0x0800)/*ADC10Sample/HoldSourceBit:
1*/
#defineINCH0(0x1000)/*ADC10InputChannelSelectBit:
0*/
#defineINCH1(0x2000)/*ADC10InputChannelSelectBit:
1*/
#defineINCH2(0x4000)/*ADC10InputChannelSelectBit:
2*/
#defineINCH3(0x8000)/*ADC10InputChannelSelectBit:
3*/
#defineCONSEQ_0(0*2u)/*Singlechannelsingleconversion*/
#defineCONSEQ_1(1*2u)/*Sequenceofchannels*/
#defineCONSEQ_2(2*2u)/*Repeatsinglechannel*/
#defineCONSEQ_3(3*2u)/*Repeatsequenceofchannels*/
#defineADC10SSEL_0(0*8u)/*ADC10OSC*/
#defineADC10SSEL_1(1*8u)/*ACLK*/
#defineADC10SSEL_2(2*8u)/*MCLK*/
#defineADC10SSEL_3(3*8u)/*SMCLK*/
#defineADC10DIV_0(0*0x20u)/*ADC10ClockDividerSelect0*/
#defineADC10DIV_1(1*0x20u)/*ADC10ClockDividerSelect1*/
#defineADC10DIV_2(2*0x20u)/*ADC10ClockDividerSelect2*/
#defineADC10DIV_3(3*0x20u)/*ADC10ClockDividerSelect3*/
#defineADC10DIV_4(4*0x20u)/*ADC10ClockDividerSelect4*/
#defineADC10DIV_5(5*0x20u)/*ADC10ClockDividerSelect5*/
#defineADC10DIV_6(6*0x20u)/*ADC10ClockDividerSelect6*/
#defineADC10DIV_7(7*0x20u)/*ADC10ClockDividerSelect7*/
#defineSHS_0(0*0x400u)/*ADC10SC*/
#defineSHS_1(1*0x400u)/*TA3OUT1*/
#defineSHS_2(2*0x400u)/*TA3OUT0*/
#defineSHS_3(3*0x400u)/*TA3OUT2*/
#defineINCH_0(0*0x1000u)/*SelectsChannel0*/
#defineINCH_1(1*0x1000u)/*SelectsChannel1*/
#defineINCH_2(2*0x1000u)/*SelectsChannel2*/
#defineINCH_3(3*0x1000u)/*SelectsChannel3*/
#defineINCH_4(4*0x1000u)/*SelectsChannel4*/
#defineINCH_5(5*0x1000u)/*SelectsChannel5*/
#defineINCH_6(6*0x1000u)/*SelectsChannel6*/
#defineINCH_7(7*0x1000u)/*SelectsChannel7*/
#defineINCH_8(8*0x1000u)/*SelectsChannel8*/
#defineINCH_9(9*0x1000u)/*SelectsChannel9*/
#defineINCH_10(10*0x1000u)/*SelectsChannel10*/
#defineINCH_11(11*0x1000u)/*SelectsChannel11*/
#defineINCH_12(12*0x1000u)/*SelectsChannel12*/
#defineINCH_13(13*0x1000u)/*SelectsChannel13*/
#defineINCH_14(14*0x1000u)/*SelectsChannel14*/
#defineINCH_15(15*0x1000u)/*SelectsChannel15*/
/*ADC10DTC0*/
#defineADC10FETCH(0x001)/*Thisbitshouldnormallybereset*/
#defineADC10B1(0x002)/*ADC10blockone*/
#defineADC10CT(0x004)/*ADC10continuoustransfer*/
#defineADC10TB(0x008)/*ADC10two-blockmode*/
#defineADC10DISABLE(0x000)/*ADC10DTC1*/
/************************************************************
*BasicClockModule
************************************************************/
#define__MSP430_HAS_BC2__/*DefinitiontoshowthatModuleisavailable*/
SFR_8BIT(DCOCTL);/*DCOClockFrequencyControl*/
SFR_8BIT(BCSCTL1);/*BasicClockSystemControl1*/
SFR_8BIT(BCSCTL2);/*BasicClockSystemControl2*/
SFR_8BIT(BCSCTL3);/*BasicClockSystemControl3*/
#defineMOD0(0x01)/*ModulationBit0*/
#defineMOD1(0x02)/*ModulationBit1*/
#defineMOD2(0x04)/*ModulationBit2*/
#defineMOD3(0x08)/*ModulationBit3*/
#defineMOD4(0x10)/*ModulationBit4*/
#defineDCO0(0x20)/*DCOSelectBit0*/
#defineDCO1(0x40)/*DCOSelectBit1*/
#defineDCO2(0x80)/*DCOSelectBit2*/
#defineRSEL0(0x01)/*Range