1、uboot在mini2440上移植uboot在2440上移植(转的 相广超老师的)默认分类 2010-11-13 09:09:26 阅读70 评论0 字号:大中小订阅 以前一直在用vivi,很精简很方便,源码很好懂,想改什么就改什么,但是功能差了点,所以移植个uboot来跑跑,uboot很好很强大,但是想搞清它的机制有点困难,先移植个最简单的试试,还没有增加对yaffs的支持和usb下载,遇到一些小问题也都解决了。我用的2440开发板,取名为TX2440。解压U-BOOT-1.1.6,进入U-BOOT目录,修改Makefile:在smdk2410_config : unconfig $(MKC
2、ONFIG) $(:_config=) arm arm920t smdk2410 NULL s3c24x0加上TX2440_config: unconfig $(MKCONFIG) $(:_config=) arm arm920t TX2440 NULL s3c24x0各项的意思如下:arm: CPU的架构(ARCH)arm920t: CPU的类型(CPU),其对应于cpu/arm920t子目录。TX2440: 开发板的型号(BOARD),对应于board/TX2440目录。NULL: 开发者/或经销商(vender)。s3c24x0: 片上系统(SOC)。在第128行:ifeq ($(ARC
3、H),arm)CROSS_COMPILE = arm-linux-指定交叉编译器,我使用的是3.4.1,这里也可以写绝对路径修改完Makefile后,在board目录下,新建自己的开发板目录TX2440,把smdk2410目录下的所有文件拷到TX2440,把smdk2410.c改为TX2440.c。修改该目录下的Makefile,把smdk2410.o改为TX2410.o。COBJS := TX2440.o flash.o将board目录下所有文件夹全部删除,只留TX2440在include/configs目录下创建板子的配置头文件,把smdk2410.h改名为TX2440.h,再把所有的文件
4、全部删除,只留TX2440.h测试能否编译成功:执行make TX2440_config出现make: execvp: /mkconfig: 权限不够查看mkconfig的权限,发现没有可执行权限,用chmod 764 mkconfig加上权限然后再make,成功后可出现 Configuring for TX2440 board.修改SDRAM配置,在board/TX2440/lowlevel_init.S中,检查#define B6_BWSCON (DW32) 位宽为32把B1_BWSCON 改为(DW16) B5_BWSCON 改为(DW8)根据HCLK设置SDRAM的刷新参数,主要是RE
5、FCNT寄存器,开发板HCLK为100M将 #define REFCNT 0x1113 改为 #define REFCNT 0x4f4增加对S3C2440的支持,2440的时钟计算公式、NAND操作和2410不太一样。对于2440开发板,将FCLK设为400MHz,分频比为FCLK:HCLK:PCLK=1:4:8。修改board/TX2440/TX2440.c中的board_init函数/* S3C2440: Mpll,Upll = (2*m * Fin) / (p * 2s) * m = M (the value for divider M)+ 8, p = P (the value for
6、 divider P) + 2*/#define S3C2440_MPLL_400MHZ (0x7f12)|(0x024)|(0x01)#define S3C2440_UPLL_48MHZ (0x3812)|(0x024)|(0x02)#define S3C2440_CLKDIV 0x05 /* FCLK:HCLK:PCLK = 1:4:8 */* S3C2410: Mpll,Upll = (m * Fin) / (p * 2s)* m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2*/#define
7、S3C2410_MPLL_200MHZ (0x5c12)|(0x044)|(0x00)#define S3C2410_UPLL_48MHZ (0x2812)|(0x01GPACON = 0x007FFFFF; gpio-GPBCON = 0x00044555; gpio-GPBUP = 0x000007FF; gpio-GPCCON = 0xAAAAAAAA; gpio-GPCUP = 0x0000FFFF; gpio-GPDCON = 0xAAAAAAAA; gpio-GPDUP = 0x0000FFFF; gpio-GPECON = 0xAAAAAAAA; gpio-GPEUP = 0x0
8、000FFFF; gpio-GPFCON = 0x000055AA; gpio-GPFUP = 0x000000FF; gpio-GPGCON = 0xFF95FFBA; gpio-GPGUP = 0x0000FFFF; gpio-GPHCON = 0x002AFAAA; gpio-GPHUP = 0x000007FF; /*support both of S3C2410 and S3C2440*/ if (gpio-GSTATUS1 = 0x32410000) | (gpio-GSTATUS1 = 0x32410002) /*FCLK:HCLK:PCLK = 1:2:4*/ clk_powe
9、r-CLKDIVN = S3C2410_CLKDIV; /* change to asynchronous bus mod */ _asm_( mrc p15, 0, r1, c1, c0, 0n /* read ctrl register */ orr r1, r1, #0xc0000000n /* Asynchronous */ mcr p15, 0, r1, c1, c0, 0n /* write ctrl register */ :r1 ); /* to reduce PLL lock time, adjust the LOCKTIME register */ clk_power-LO
10、CKTIME = 0xFFFFFF; /* configure MPLL */ clk_power-MPLLCON = S3C2410_MPLL_200MHZ; /* some delay between MPLL and UPLL */ delay (4000); /* configure UPLL */ clk_power-UPLLCON = S3C2410_UPLL_48MHZ; /* some delay between MPLL and UPLL */ delay (8000); /* arch number of SMDK2410-Board */ gd-bd-bi_arch_nu
11、mber = MACH_TYPE_SMDK2410; else /* FCLK:HCLK:PCLK = 1:4:8 */ clk_power-CLKDIVN = S3C2440_CLKDIV; /* change to asynchronous bus mod */ _asm_( mrc p15, 0, r1, c1, c0, 0n /* read ctrl register */ orr r1, r1, #0xc0000000n /* Asynchronous */ mcr p15, 0, r1, c1, c0, 0n /* write ctrl register */ :r1 ); /*
12、to reduce PLL lock time, adjust the LOCKTIME register */ clk_power-LOCKTIME = 0xFFFFFF; /* configure MPLL */ clk_power-MPLLCON = S3C2440_MPLL_400MHZ; /* some delay between MPLL and UPLL */ delay (4000); /* configure UPLL */ clk_power-UPLLCON = S3C2440_UPLL_48MHZ; /* some delay between MPLL and UPLL
13、*/ delay (8000); /* arch number of SMDK2440-Board */ gd-bd-bi_arch_number = MACH_TYPE_S3C2440; /* adress of boot parameters */ gd-bd-bi_boot_params = 0x30000100; icache_enable(); dcache_enable(); return 0;在cpu/arm920t/s3c24X0/speed.c中修改:在程序开头增加一行DECLARE_GLOBAL_DATA_PTR;,这样才可以使用gd变量修改get_PLLCLK函数:sta
14、tic ulong get_PLLCLK(int pllreg) S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); ulong r, m, p, s; if (pllreg = MPLL) r = clk_power-MPLLCON; else if (pllreg = UPLL) r = clk_power-UPLLCON; else hang(); m = (r & 0xFF000) 12) + 8; p = (r & 0x003F0) 4) + 2; s = r & 0x3; /* support
15、 both of S3C2410 and S3C2440 */ if (gd-bd-bi_arch_number = MACH_TYPE_SMDK2410) return(CONFIG_SYS_CLK_FREQ * m) / (p s); else return(CONFIG_SYS_CLK_FREQ * m * 2) / (p s); /* S3C2440 */修改get_HCLK, get_PCLK:/* for s3c2440 */#define S3C2440_CLKDIVN_PDIVN (10)#define S3C2440_CLKDIVN_HDIVN_MASK (31)#defin
16、e S3C2440_CLKDIVN_HDIVN_1 (01)#define S3C2440_CLKDIVN_HDIVN_2 (11)#define S3C2440_CLKDIVN_HDIVN_4_8 (21)#define S3C2440_CLKDIVN_HDIVN_3_6 (31)#define S3C2440_CLKDIVN_UCLK (13)#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf0)#define S3C2440_CAMDIVN_CAMCLK_SEL (14)#define S3C2440_CAMDIVN_HCLK3_HALF (18)#defi
17、ne S3C2440_CAMDIVN_HCLK4_HALF (19)#define S3C2440_CAMDIVN_DVSEN (1bd-bi_arch_number = MACH_TYPE_SMDK2410) return(clk_power-CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK(); else clkdiv = clk_power-CLKDIVN; camdiv = clk_power-CAMDIVN; /* work out clock scalings */ switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MAS
18、K) case S3C2440_CLKDIVN_HDIVN_1: hdiv = 1; break; case S3C2440_CLKDIVN_HDIVN_2: hdiv = 2; break; case S3C2440_CLKDIVN_HDIVN_4_8: hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4; break; case S3C2440_CLKDIVN_HDIVN_3_6: hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3; break; return get_FCLK()
19、 / hdiv; /* return PCLK frequency */ulong get_PCLK(void) S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); unsigned long clkdiv; unsigned long camdiv; int hdiv = 1; /* support both of S3C2410 and S3C2440 */ if (gd-bd-bi_arch_number = MACH_TYPE_SMDK2410) return(clk_power-CLKDIVN
20、& 0x1) ? get_HCLK()/2 : get_HCLK(); else clkdiv = clk_power-CLKDIVN; camdiv = clk_power-CAMDIVN; /* work out clock scalings */ switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) case S3C2440_CLKDIVN_HDIVN_1: hdiv = 1; break; case S3C2440_CLKDIVN_HDIVN_2: hdiv = 2; break; case S3C2440_CLKDIVN_HDIVN_4_8: hd
21、iv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4; break; case S3C2440_CLKDIVN_HDIVN_3_6: hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3; break; return get_FCLK() / hdiv / (clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1); 重新执行make TX2440_config make all 生成u-boot.bin,由于还没有增加NAND Flash的支持,所以可烧入NOR Flash中
22、运行在make all时会出现错误:没有CAMDIVN这个要在include/s3c24x0.h中定义, 在129行S3C24X0_CLOCK_POWER结构体中增加:S3C24X0_REG32 CAMDIVN; /* for s3c2440*/支持NAND Flash首先在配置文件include/configs/TX2440.h的宏CONFIG_COMMANDS中增加CFG_CMD_NAND (大概在82行)编译,出现nand.c的错误和警告解决:在include/configs/TX2440.h的最后面增加3个宏:/*NAND flash settings*/#define CFG_NAN
23、D_BASE 0 /无实际意义:基地址,在board_nand_init中重新定义#define CFG_MAX_NAND_DEVICE 1 /NAND Flash设备数目为1#define NAND_MAX_CHIPS 1 /每个NAND设备由1个NADN芯片组成修改配置文件后再编译,只有一个错误了“board_nand_init”函数未定义board_nand_init需要自己编写,在cpu/arm920t/s3c24x0下新建nand_flash.c编写之前,需要针对S3C2440 NAND Flash定义一些数据结构和函数在include/s3c24x0.h中增加S3C2440_NAN
24、D数据结构(168行)/* NAND FLASH (see S3C2440 manual chapter 6) */typedef struct S3C24X0_REG32 NFCONF; S3C24X0_REG32 NFCONT; S3C24X0_REG32 NFCMD; S3C24X0_REG32 NFADDR; S3C24X0_REG32 NFDATA; S3C24X0_REG32 NFMECCD0; S3C24X0_REG32 NFMECCD1; S3C24X0_REG32 NFSECCD; S3C24X0_REG32 NFSTAT; S3C24X0_REG32 NFESTAT0; S3C24X0_REG32 NFESTAT1; S3C24X0_REG32 NFMECC0; S3C24X0_REG32 NFMECC1; S3C24X0_REG32 NFSECC; S3C24X0_REG32 NFSBLK; S3C24X0_REG32 NFEBLK; /*_attribute_(_packed_)*/ S3C2440_NAND;在include/s3c
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