Verilog程序代码集.docx
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Verilog程序代码集
1.全加器
Sum=A⊕B⊕Cin
Count=AB+Cin(A+B)
数据流
moduleadder(a,b,Cin,Sum,Count);
input[2:
0]a,b;
inputCin;
output[2:
0]Sum;
outputCount;
assign{Count,Sum}=a+b+Cin;
endmodule
行为描述always语句
moduleadder(a,b,c,Cin,Sum,Count);
input[4:
0]a,b;
inputCin;
outputreg[4:
0]Sum;
outputregCount;
regT1,T2,T3;
always@(aorborCin)
begin
Sum=a^b^Cin;
T1=A&B;
T2=Cin&A;
T3=Cin&B;
Count=T1|T2|T3;
end
endmodule
结构体
moduleadder(a,b,Cin,Sum,Count);
inputa,b,Cin;
outputSum,Count;
Xora1(s1,a1,b);
Xora2(Sum,s1,Cin);
anda3(T1,a,b);
ora4(T2,a,b);
anda5(T3,Cin,T2);
ora6(Count,T1,T3);
Endmodule
2.数值比较器
判断两值是否相等
modulecompare(a,b,equal);
input[7:
0]a,b;
outputequal;
assignequal=(a==b)?
|0;
endmodule
谁大谁输出
modulecompare(a,b,out);
input[7:
0]a,b;
outputreg[7:
0]out;
always@(aorb)
begin
if(a>b)out<=a;
elseif(a==b)out<=a;
else out<=b;
end
endmodule
输出参数
modulecompare(a.b.xgy,xsy,xey);
input[7:
0]x,y;
outputregxgy,xsy,xey;
always@(xory)
begin
if(x==y) xey=1;
else xey=0;
if(x>y) beginxgy=1;xsy=0;end
elseif(xend
endmodule
3.编码器(4-28-316-4编码)
case语句8-3编码(优先)
modulecode(in,out);
input[7:
0]in;
outputreg[2:
0]out;
always@(in)
casex(in)
beginf=1;8’b1xxxxxxx:
out=3’b111;end
beginf=1;8’b01xxxxxx:
out=3’b110;end
beginf=1;8’b001xxxxx:
out=3’b101;end
beginf=1;8’b0001xxxx:
out=3’b100;end
beginf=1;8’b00001xxx:
out=3’b011;end
beginf=1;8’b000001xx:
out=3’b010;end
beginf=1;8’b0000001x:
out=3’b001;end
beginf=1;8’b00000001:
out=3’b000;end
default:
beginf=0:
out=3’b000;end
endcase
endmodule
if-else语句(4-2优先编码)
modulecode(in,out);
input[3:
0]in;
outputreg[1:
0]out;
always@(in)
if(in[3]==1):
beginf=1;out=2’b11;end
elseif(in[2]==1):
beginf=1;out=2’b10;end
elseif(in[1]==1):
beginf=1;out=2’b01;end
elseif(in[0]==1):
beginf=1;out=2’b00;end
elsebeginf=0;out=2’b00;end
endmodule
4.多路选择器
行为描述(4选1)
modulechoice(A,B,C,D,ncsaddrout);
input[7:
0]A,B,C,D;
inputncs;
input[1:
0]addr;
outputreg[7:
0]out;
always@(AorBorCorDorncsoraddr)
begin
if(!
ncs)
case(addr)
2’b00:
out=A;
2’b01:
out=B;
2’b10:
out=C;
2’b11:
out=D;
endcase
else out=0;
end
endmodule
5.设计一个4位双向移位寄存器。
moduleshift(sout,out,clk,in,sin,d,load);
inputclk,sin,d,load;input[3:
0]in;
outputsout;output[3:
0]out;
reg[3:
0]out;
always@(posedgeclk)
if(load)out<=in;
else
if(d==0)
beginout<=out>>1;out[3]<=sin;sout<=out[0];end
else
beginout<=out<<1;out[0]<=sin;sout<=out[3];end
endmodule
6.11111010000序列检测器
moduleshift(q,s,d,clk);
output[11:
0]q;
outputs;
inputd;
inputclk;
reg[11:
0]q;
regs;
always@(posedgeclk)
begin
q<=q<<1;q[0]<=d;
end
always@(posedgeclk)
if(q==12'b11111010000)
s<=1;
else
s<=0;
Endmodule
7.计数器
计数分频器
8分频占空比1:
1
modulediv(clk8,clk,rst);
inputclk,rst;
outputregclk8;
reg[2:
0]count;
always@(posedgeclk)
begin
if(rst)begin
clk8<=0;count<=0;end
elsebegin
if(count==7)count<=0;
else count<=count+1;
if(count<=3)clk_8<=0;
else clk_8<=1;
end
end
endmodule
预置数计数
modulesetcount(clk,rst,F,out);
inputclk,rst,F;
outputregout;reg[3:
0]count;
always@(posedgeclkorposedgerst)
begin
if(rst)beginout<=0;count<=0;end
elseif(F==1) count<=10;
elseif(count>=15)begin
Count<=o;out<=1;end
elsebegin
count<=count+1;out<=0;end
end
endmodule
8.触发器
T=1时翻转
T触发器
T=0时保持翻转
moduleD_FF(T,clk,rst,Q,Qn);
inputT,clk,rst;
outputregQ,Qn;
always@(posedgeclkorposedgerst)
if(rst)begin
Q<=0;Qn<=1;end
elseif(T) begin
Q<=~Q Qn<=~Qn;end
else begin
Q<=Q;Qn<=Qn;end
endmodule
D触发器Qn+1=D(保持D)
moduleD_FF(D,clk,rst,Q,Qn);
inputD,clk,rst;
outputregQ,Qn;
always@(posedgeclkorposedgerst)
ef(rst)beginQ<=0;Qn<=1;end
else beginQ<=D;Qn<=~D;end
endmodule
J=1K=0时Q=1置1
J=0K=1时Q=0置0
J=K=0时Q=Q保持
J=K=1时Q=~Q取反转
JK触发器
moduleJK_FF(J,K,clk,rst,Q,Qn);
inputJ,K,clk,rst;
outputQ,Qn;
always@(posedgeclkorposedgerst)
if(rst) begin
Q<=0;Qn<=1end
elseif(J==1&&K==0)begin
Q<=1;Qn<=0;end
elseif((J==0&&K==1)begin
Q<=0;Qn<=1;end
elseif((J==0&&K==0)begin
Q<=Q;Qn<=Qn;end
else begin
Q<=~Q;Qn=~Qn; end
endmodule
9.测试程序(异或门测试)
‘timescale 1ns/1ps