VCS后缀选项说明.docx
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VCS后缀选项说明
一、VCS简介
VCS（VerilogCompiledSimulator）定位于大型、复杂电路的快速仿真，主要用于Verilog源代码的编译仿真，但也能对VHDL、C/C++源代码进行混合仿真。
VCS支持命令行方式（CLI），为了进行图形界面调试，VCS包含了一个图形仿真器VirSim（VirtualSimulatorEnvironment），下面主要讲述VirSim的使用。
二、VCS的简单CLI命令
在VCS的CLI方式下，输入的所有命令都以vcs开头。
vcs-h帮助命令，列表显示vcs后可跟的所有命令选项及简单解释；
vcs-RIRunInteractive.StartsVirSim
immediatelyaftercompilation;
vcs-lineEnablessteppingthroughthecodeandsourcelinebreakpointsinVirSim;
vcs+cli+1|2|3|4+cliEnableCLIdebugging,
1enablesyoutoseethevaluesofnetsandregistersanddepositvaluestoregisters;
2alsoenablesbreakpointsonvaluechangesofnetsandregisters;
3alsoenablesyoutoforceavalueonnets;
4alsoenablesyoutoforceavalueonaregister;
vcs-MupdateEnableincrementalcompilationand
overwritethemakefile;
vcs–MEnableincrementalcompilation,but
donotoverwritethemakefile;
vcs–fSpecifiesafilethatcontainsalistof
pathnamestosourcefilesand
compile-timeoptions;
vcs-iSpecifiesafilecontainingCLI
commandsthatVCSexecuteswhensimulationstarts;
VCS是Synopsys公司的仿真工具.
VCS对verilog模型进行仿真包括两个步骤:
1.编译verilog文件成为一个可执行的二进制文件命令为:
$>vcssource_files
2.运行该可执行文件
$>./simv
类似于NC,也有单命令行的方式:
$>vcssource_files-R
-R命令表示,编译后立即执行.
下面讲述常用的命令选项:
-cmline|cond|fsm|tgl|obc|path 设定coverage的方式
+define+macro=value+ 预编译宏定义
-ffilename RTL文件列表
+incdir+directory+ 添加include文件夹
-I 进入交互界面
-l logfile文件名
-Ppli.tab 定义PLI的列表（Tab）文件
+v2k 使用推荐的标准
-y 定义verilog的库
-notice 显示详尽的诊断信息
-o 指定输出的可执行文件的名字,缺省是sim.v
zz51life
∙Summaryofvcscompileoptions:
-------------------------------
-ASFLAGS"opts" pass'opts'totheassembler
-B generatelongcallinstructionsinnativeassemblycode（HPonly）
-CC"opts" pass'opts'toCcompiler
-CFLAGS"opts" pass'opts'toCcompiler
-LDFLAGS"opts" pass'opts'toCcompileronloadlineonly
-I enableinteractive/postprocessingdebuggingcapabilities
-ID gethostidentificationinformation
-M enableincrementalcompilation（seemanual）
-Mupdate enableincrementalcompilationandkeeptheMakefileup-to-date
-Marchive[=N] createintermediatelibstoreducelinklinelength;Nobjsperlib
-Pplitab compilesuser-definedplidefinitiontable'plitab'
-PP enableoptimizerpostprocessingcapabilitiesforvcd+
-R aftercompilation,runsimulationexecutable
-RI aftercompilation,runsimulationunderxvcs（Implies-I）
-RIG runsimulationunderxvcswithoutcompiling（executablehastoexist）
-RPP runxvcsinpostprocessingmode（requiresfilecreatedbyvcdpluson）
-V[t] verbosemode;with't',includetimeinformation
-asfoo usefooastheassembler
-ccfoo usefooastheCcompiler
-cppfoo usefooastheC++compiler
-e specifythenameofyourmain（）routine.
（seemanualsection7-11formoredetails）.
-ffile reads'file'forotheroptions
-gen_c generateCcode（forHPandSun,defaultis-gen_obj）
-gen_asm generatenativeassemblycode（HPandSunonly）
-gen_obj generatenativeobjectcode（HPandSunonly）
-ldfoo usefooasthelinker.（refervcsmanualforcompatibilitywith-cppoption）
-line enablesingle-stepping/breakpointsforsourceleveldebugging
-lmc-swift includelmcswiftinterface
-lmc-hm includelmchardwaremodelerinterface
-vera addVERA4.5+libraries
-vera_dbind addVERA4.5+librariesfordynamicbinding
-location displayfullpathnametovcsinstallationforthisplatform
-vhdlobj generateavhdlobjforsimulatinginavhdldesign
-mixedhdl includeMixedHDL-1.0interface
-mhdl includeMixedHDL-2.0interfaceandlibrary
-q quietmode
-platform displaynameofvcsinstallationsubdirectoryforthisplatform
-syslib'libs' specifysystemlibraries（placedlastonthelinkline）eg-lm
-oexec nametheexecutablesimulationmodel'exec'（defaultis'simv'）
-u treatallnontextstringcharactersasuppercase
-vfile searchforunresolvedmodulereferencesin'file'
-ylibdir searchforunresolvedmodulereferencesindirectory'libdir'
+acc enablepliapplicationstouseaccroutines（seemanual）
+ad includeanlogsimulationinterfaceandlibrary
+adfmi="files" ADFMIsupportforvcs-ace
+cliedit enablecommandlineedit/recall（seedoc/readline.ps）
+cli enablecommandlineinteractivedebugging（seemanual）
+cmod Enablingcmodulefeature
+cmodext+cmodext Changingcmoduleextensiontocmodext
+cmodincdir+cmoddir CmoduleIncludedirectory
+cmoddefine+macro definecmodulesource'macro'intheformofXX=YY
+define+macro definehdlsource'macro'tohavevalue"macro"
+plusarg_save hardwiretheplusargs,whichfollowthisflag,intosimv
+plusarg_ignore turnoff+plusarg_save
+prof tellsvcstoprofilethethedesignandgeneratevcs.proffile
+race tellsvcstogenerateareportofallraceconditionsduringsimulation
andwritethisreportintherace.outfile
+rad+1 enablelevel1radiantoptimizations（SeeReleaseNotes）
+rad+2 enablelevel2radiantoptimizations（SeeReleaseNotes）
+libext+lext useextension'lext'whensearchinglibrarydirectorys
+librescan searchfrombeginningoflibrarylistforallundefinedmods
+incdir+idir for`includefiles,searchdirectory'idir'
+nospecify suppresspathdelaysandtimingchecks
+notimingchecks suppresstimingchecks
+optconfigfile+foouse'foo'astheoptimizationconfigfile（SeeReleaseNotes）
+vcsd enabletheVCSDirectsimkernelinterface
-cmhelp enableCoverMeterhelp.CoverMetershouldbeinstalled
andenvironmentvariableCM_HOMEshouldbeset.
-cm enableVCStofirstruncmSourcetoinstrumentthe
Verilogsourcefilesonthecommandline,andthento
compiletheinstrumentedsourcefiles
-cm_all enableVCStolinkCoverMeterintotheVCSexecutableina waythatenablesline,condition,andFSMcoverageand establishesthedirectlink.Enablingalltypesofcoverage andthedirectlinkisthedefaultconditionwhenyou includethe-cmoptionsoyoucanomitthisoption
-cm_lineonly enableVCStolinkCoverMeterintotheVCSexecutable inawaythatonlyenableslinecoveragewhenitalso establishesthedirectlink.Usethisoptionforfaster simulationandwhenyouonlyneedlinecoverage
Compile-TimeOptions
********************
-f
Specifiesafilethatcontainsalistofpathnamestosourcefiles
andcompile-timeoptions.
-F
Sameasthe-foptionbutallowsyoutospecifyapathtothefile
andthesourcefileslistedinthefiledonothavetobeabsolute
pathnames.
-h
Displaysasuccinctdescriptionofthemostcommonlyusedcompile-time
andruntimeoptions.
-l
（lowercaseL）SpecifiesalogfilewhereVCSrecordscompilation
messagesandruntimemessagesifyouincludethe-R,-RI,or
-RIGoptions.
-line
EnablessteppingthroughthecodeandsourcelinebreakpointsinVirSim.
-M
Enablesincrementalcompilation,butdonotoverwritethemakefile.
-Mupdate
Enableincrementalcompilationandoverwritethemakefile.
-notice
Enablesverbosediagnosticmessages.
-o
Specifiesthenameoftheexecutablefilethatistheproductof
compilation.Thedefaultnameissimv（simv.exeonWindows）.
-ova_cov
Enablesfunctionalcoverage.
-P
SpecifiesaPLItablefile.
-R
RuntheexecutablefileimmediatelyafterVCSlinkstogetherthe
executablefile.Youcanaddanyruntimeoptiontothevcscommand
line.
-s
Stopsimulationjustasitbegins.Usethisoptionwiththe-Rand
+clioptions.
-timescale=/
Ifonlysomesourcefilescontainthe`timescalecompilerdirective
andtheonesthatdon'tappearfirstonthevcscommandline,use
thisoptiontospecifythetimescaleforthesesourcefiles.
-V
Enablestheverbosemode.
-v
SpecifiesaVeriloglibraryfiletosearchformoduledefinitions.
-vera
SpecifiesthestandardVERAPLItablefileandobjectlibrary.
-y
SpecifiesaVeriloglibrarydirectorytosearchformodule
definitions.
+2state
Enables2statesimulation.
+cli+[=]1|2|3|4
EnableCLIdebugging.
1enablesyoutoseethevaluesofnetsandregistersanddeposit
valuestoregisters.
2alsoenablesbreakpointsonvaluechangesofnetsandregisters.
3alsoenablesyoutoforceavalueonnets.
4alsoenablesyoutoforceavalueonaregister.
YoucanspecifyamoduletoenableCLIdebuggingonlyforinstances
ofthemodule.
+define+=
Definesatextmacro.TestforthisdefinitioninyourVerilog
sourcecodeusingthe`ifdefcompilerdirective.
+incdir+
Specifiesthedirectoriesthatcontainthefilesyouspecifiedwith
the`includecompilerdirective.Youcanspec
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