EDA设计参考程序完整版合计31题.docx
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EDA设计参考程序完整版合计31题
1、设计一个带计数使能、异步复位、带进位输出的减1三位二进制计数器，结果由共阴极七段数码管显示。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounteris
port（clk,en,clr:
instd_logic;
ledout:
outstd_logic_vector（6downto0）;
co:
outstd_logic）;
endcounter;
architectureaofcounteris
signalcnt:
std_logic_vector（2downto0）;
signalhex:
std_logic_vector（2downto0）;
begin
process（clk）
begin
ifclr='1'then
cnt<=（others=>'0'）;
elsif（clk'eventandclk='1'）then
ifen='1'then
ifcnt="000"then
cnt<="111";
co<='1';
else
cnt<=cnt-'1';
co<='0';
endif;
endif;
endif;
endprocess;
hex<=cnt（2downto0）;
withhexselect
ledout<="0000111"when"111",
"1111101"when"110",
"1101101"when"101",
"1100110"when"100",
"1001111"when"011",
"1011011"when"010",
"0000110"when"001",
"0111111"whenothers;
enda;
2、设计一个带计数使能、同步复位、带进位输出的增1十进制计数器，计数结果由共阴极七段数码管显示。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcounter3IS
PORT（clk,clr,en:
INSTD_LOGIC;
co:
OUTSTD_LOGIC;
ledout:
OUTSTD_LOGIC_VECTOR（6downto0））;
ENDcounter3;
ARCHITECTUREaOFcounter3IS
SIGNALcnt:
STD_LOGIC_VECTOR（3downto0）;
SIGNALled:
STD_LOGIC_VECTOR（6downto0）;
BEGIN
PROCESS（clk）
BEGIN
IF（clk'EVENTANDclk='1'）THEN
IFclr='1'THEN
cnt<=（OTHERS=>'0'）;
ELSIFEN='1'THEN
IFcnt="1001"THEN
cnt<="0000";
co<='1';
ELSE
cnt<=cnt+'1';
co<='0';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
ledout<=NOTled;
WITHcntSELECT
led<="1111001"WHEN"0001",--1
"0100100"WHEN"0010",--2
"0110000"WHEN"0011",--3
"0011001"WHEN"0100",--4
"0010010"WHEN"0101",--5
"0000010"WHEN"0110",--6
"1111000"WHEN"0111",--7
"0000000"WHEN"1000",--8
"0010000"WHEN"1001",--9
"1000000"WHENothers;--0
ENDa;
3、设计一个带计数使能、异步复位、同步装载的可逆三位二进制计数器，计数结果由共阴极七段数码管显示。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycounteris
port（clk,clr,en,stld,upon:
instd_logic;
din:
instd_logic_vector（2downto0）;
q:
outstd_logic_vector（6downto0））;
endcounter;
architectureaofcounteris
signalcnt:
std_logic_vector（2downto0）;
signaly:
std_logic_vector（6downto0）;
begin
process（clk）
begin
ifclr='1'then
cnt<="000";
elsifclk'eventandclk='1'then
ifstld='1'then
cnt<=din;
elsifen='1'then
ifupon='0'then
cnt<=cnt-'1';
else
cnt<=cnt+'1';
endif;
endif;
endif;
endprocess;
q<=NOTy;
WITHcntSELECT
y<="1111001"WHEN"001",--1
"0100100"WHEN"010",--2
"0110000"WHEN"011",--3
"0011001"WHEN"100",--4
"0010010"WHEN"101",--5
"0000010"WHEN"110",--6
"1111000"WHEN"111",--7
"1000000"WHENothers;--0
enda;
4、设计一个带计数使能、同步复位、异步装载、可逆计数的通用计数器。
计数结果由共阴极七段数码管显示。
entityasdasdsadxvzzxis
Generic（count_value:
INTEGER:
=9）;
Port（clk:
inSTD_LOGIC;
clr:
inSTD_LOGIC;
en:
inSTD_LOGIC;
load:
inSTD_LOGIC;
dir:
inSTD_LOGIC;
data_in:
inINTEGERRANGE0TOcount_value;
ledout:
outSTD_LOGIC_VECTOR（6downto0））;
endasdasdsadxvzzx;
architectureBehavioralofasdasdsadxvzzxis
SIGNALcnt:
INTEGERRANGE0TOcount_value;
SIGNALled:
STD_LOGIC_VECTOR（6DOWNTO0）;
begin
PROCESS（load,clk）
begin
IFload='1'THEN
cnt<=data_in;
ELSIF（clk'eventandclk='1'）THEN
IFclr='1'then
cnt<=0;
elsifen='1'then
ifdir='1'then
ifcnt=count_valuethen
cnt<=0;
else
cnt<=cnt+1;
endif;
else
ifcnt=0then
cnt<=count_value;
else
cnt<=cnt-1;
endif;
endif;
endif;
endif;
endprocess;
ledout<=NOTled;
withcntselect
led<="1111001"WHEN1,--1
"0100100"WHEN2,--2
"0110000"WHEN3,--3
"0011001"WHEN4,--4
"0010010"WHEN5,--5
"0000010"WHEN6,--6
"1111000"WHEN7,--7
"0000000"WHEN8,--8
"0010000"WHEN9,--9
"1000000"WHEN0,--0
"1111111"WHENothers;
endBehavioral;
5、设计一个具有16分频、8分频、4分频和2分频功能的分频器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityclkdivis
port（clk:
instd_logic;
clk_div2:
outstd_logic;
clk_div4:
outstd_logic;
clk_div8:
outstd_logic;
clk_div16:
outstd_logic）;
endclkdiv;
architecturertlofclkdivis
signalcount:
std_logic_vector（3downto0）;
begin
process（clk）
begin
if（clk'eventandclk='1'）then
if（count="1111"）then
count<=（others=>'0'）;
else
count<=count+1;
endif;
endif;
endprocess;
clk_div2<=count（0）;
clk_div4<=count
（1）;
clk_div8<=count
（2）;
clk_div16<=count（3）;
endrtl;
法二
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdiv4IS
PORT（clk:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR（3DOWNTO0）;
reset:
INSTD_LOGIC;
fout:
OUTstd_LOGIC）;
ENDdiv4;
ARCHITECTUREaOFdiv4IS
begin
process（clk）
variablecnt:
std_logic_vector（3downto0）:
="0000";
begin
ifreset='1'then
fout<='0';
elsif（clk'eventandclk='1'）then
ifcnt="1111"then
cnt:
="0000";
else
cnt:
=cnt+'1';
endif;
ifdin="0000"then
fout<=cnt（3）;
elsifdin="1000"then
fout<=cnt
（2）;
elsifdin="1100"then
fout<=cnt
（1）;
elsifdin<="1110"then
fout<=cnt（0）;
else
fout<='1';
endif;
endif;
endprocess;
enda;
6、设计一个正负脉宽相等的通用分频器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcounterIS
GENERIC（count_value:
INTEGER:
=15）;
PORT（clk,clr,en:
INSTD_LOGIC;
count:
OUTSTD_LOGIC）;
ENDcounter;
ARCHITECTUREaOFcounterIS
SIGNALcnt:
INTEGERRANGE0TOcount_value;
SIGNALco:
STD_LOGIC;
SIGNALcount1:
STD_LOGIC;
BEGIN
PROCESS（clk,clr）
BEGIN
IFclr='1'THEN
cnt<=0;
ELSIF（clk'EVENTANDclk='1'）THEN
IFen='1'THEN
IFcnt=count_valueTHEN
cnt<=0;
co<='1';
ELSE
cnt<=cnt+1;
co<='0';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS（co）
BEGIN
IF（co'EVENTANDco='1'）THEN
count1<=NOTcount1;
ENDIF;
count<=count1;
ENDPROCESS;
ENDa;
法二：
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdivIS
GENERIC（num:
INTEGER:
=2）;
PORT
（clk:
INSTD_LOGIC;
reset:
INSTD_LOGIC;
co:
OUTSTD_LOGIC）;
ENDdiv;
ARCHITECTURErtlOFdivIS
BEGIN
PROCESS（clk）
VARIABLEcnt:
STD_LOGIC_VECTOR（numdownto0）:
=（others=>'0'）;
BEGIN
IFreset='1'thenco<='0';
ELSIF（clk'eventandclk='1'）THEN
cnt:
=cnt+'1';
ENDIF;
co<=cnt（num）;
ENDPROCESS;
ENDrtl;
7、设计一个正负脉宽可控的4分频的分频器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdivIS
PORT（clk,rst:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR（1DOWNTO0）;
COUNT:
OUTSTD_LOGIC）;
ENDdiv;
ARCHITECTURErtlOFdivIS
SIGNALco:
STD_LOGIC;
BEGIN
PROCESS（clk）
VARIABLEcnt:
STD_LOGIC_VECTOR（1DOWNTO0）;
BEGIN
ifrst='1'then
co<='0';
cnt:
="00";
elsif（clk'eventandclk='1'）then
if（cnt="11"）then
cnt:
="00";
co<=notco;
elsif（cnt=din）then
co<=notco;
cnt:
=cnt+'1';
else
cnt:
=cnt+'1';
endif;
endif;
endprocess;
count<=co;
endrtl;
8根据需要设计一个分频器：
可以控制实现四种分频形式：
第一种：
5分频、第二种：
8分频、
第三种：
15分频、第四种：
16分频
（其中8分频和16分频为正负脉宽相等的分频器）
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfenpinis
port（clk:
instd_logic;
en:
instd_logic_vector（1downto0）;
cout:
outstd_logic）;
endfenpin;
architecturedgnfenpinoffenpinis
signalhex:
std_logic_vector（3downto0）;
begin
process（clk）
variablecnt:
std_logic_vector（3downto0）;
begin
if（clk'eventANDclk='1'）then
if（en="00"）then
if（cnt>="0111"）then
cnt:
="0000";--8分频
else
cnt:
=cnt+'1';
endif;
cout<=cnt
（2）;
elsif（en="01"）then
if（cnt>="0100"）then
cnt:
="0000";--5分频
cout<='1';
else
cnt:
=cnt+'1';
cout<='0';
endif;
elsif（en="10"）then
if（cnt>="1110"）then
cnt:
="0000";cout<='1';
else
cnt:
=cnt+'1';cout<='0';--15分频
endif;
else
if（cnt>="1111"）then
cnt:
="0000";--16分频
else
cnt:
=cnt+'1';
endif;
cout<=cnt（3）;
endif;
endif;
endprocess;
enddgnfenpin;
9、设计一个M序列发生器，M序列为“11110101”
LIBRARYIEEE;
USEIEEE.STD_logic_1164.all;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
entityseqis
Port（clk:
inSTD_LOGIC;
fout:
outSTD_LOGIC）;
endseq;
architectureBehavioralofseqis
signalcnt:
std_logic_vector（2downto0）;
begin
process（clk）
begin
if（clk'eventandclk='1'）then
ifcnt="111"then
cnt<="000";
else
cnt<=cnt+'1';
endif;
endif;
endprocess;
withcntselect
fout<='1'when"000",
'1'when"001",
'1'when"010",
'1'when"011",
'0'when"100",
'1'when"101",
'0'when"110",
'1'whenothers;
endBehavioral;
10、设计一个彩灯控制器，彩灯共有6个，每次顺序点亮相邻的2个彩灯，
如此循环执行，循环的方向可以控制
LIBRARYIEEE;
USEIEEE.STD_logic_1164.all;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
entitycaidengis
Port（clk:
inSTD_LOGIC;
rl:
inSTD_LOGIC;
ledout:
outSTD_LOGIC_VECTOR（5downto0））;
endcaideng;
architectureBehavioralofcaidengis
signalled:
STD_LOGIC_VECTOR（5downto0）:
=（others=>'0'）;
signalk:
STD_LOGIC:
='0';
begin
process（clk）
begin
if（clk'eventandclk='1'）then
if（k='0'）then
led<=（0=>'0',1=>'0',others=>'1'）;
k<='1';
elsif（rl='1'）then
led<=led（4downto0）&led（5）;
elsif（rl='0'）then
led<=led（0）&led（5downto1）;
endif;
endif;
ledout<=led;
endprocess;
endBehavioral;
11、设计一个具有左移、右移控制，同步并行装载和串行装载的4位串行移位寄存器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYshifter1IS
PORT（clk,clr,ser,dir,stld:
INSTD_LOGIC;
din:
INSTD_LOGIC_VECTOR（0TO3）;
qh:
OUTSTD_LOGIC_VECTOR（0TO3））;
ENDshifter1;
ARCHITECTURErt1OFshifter1IS
SIGNALreg:
STD_LOGIC_VECTOR（0TO3）:
=（others=>'0'）;
begin
process（clk,clr）
begin
ifclr='1'then
reg<=（others=>'0'）;
elsifclk'eventandclk='1'then
ifstld='0'then
reg<=din;
else
if（dir='0'）then
reg<=reg（1to3）&ser;qh<=reg（0）;
else
reg<=ser®（0to2）;qh<=reg（3）;
endif;
endif;
endif;
endprocess;
endrt1;
12、设计一个4人表决电路，参加表决者为4人，同意为1，不同意为0，同意者过半则表决通过，
绿指示灯亮，表决不通过则红指示灯亮。
同意与不同意人数相等时，两灯同时亮起。
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