4位的十进制的数字频率计.docx
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4位的十进制的数字频率计
--VHDL频率计
--一个有效位为4位的十进制的数字频率计。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityfreqis
port(fsin:
instd_logic;--被测信号
clk:
instd_logic;--基准时间,1Hz
reset:
instd_logic;
show:
outstd_logic_vector(6downto0);--数码管段码输出
row:
outstd_logic_vector(3downto0));--数码管选择信号
endfreq;
architectureoneoffreqis
signaltest_en:
std_logic;
signalclear:
std_logic;--复位信号
signaldata:
std_logic_vector(15downto0);--bcd
signaldata_in:
std_logic_vector(3downto0);--单个数码管显示
signalrow_in:
std_logic_vector(3downto0);--数码管的选择
begin
process(clk)
begin
ifclk'eventandclk='1'then
test_en<=nottest_en;
endif;
endprocess;
clear<=notclkandnottest_en;--定义clear信号
process(fsin)
begin
ifreset='1'then
row_in<="0001";
elsiffsin'eventandfsin='1'then
ifrow_in="0001"thenrow_in<="0010";
elsifrow_in="0010"thenrow_in<="0100";
elsifrow_in="0100"thenrow_in<="1000";
elsifrow_in="1000"thenrow_in<="0001";
endif;
endif;
endprocess;
--在1秒钟时间内对被测脉冲信号计数
process(fsin,test_en)
begin
ifclear='1'thendata<="00000";
elsiffsin'eventandfsin='1'then
iftest_en='1'then
ifdata(15downto0)="11001"thendata<=data+"00111";
--9999->0000
elsifdata(11downto0)="1"thendata<=data+"1";
--999->1000
elsifdata(7downto0)="10011001"thendata<=data+"01100111";
--99->100
elsifdata(3downto0)="1001"thendata<=data+"0111";
--9->10
elsedata<=data+'1';
endif;
endif;
endif;
endprocess;
--根据所选数码管显示数据
process(row_in)
begin
row(3downto0)<=row_in(3downto0);
caserow_inis
when"0001"=>data_in<=data(3downto0);
when"0010"=>data_in<=data(7downto4);
when"0100"=>data_in<=data(11downto8);
when"1000"=>data_in<=data(15downto12);
whenothers=>data_in<="XXXX";
endcase;
endprocess;
--根据欲显示的数据配置数码管
process(data_in)
begin
casedata_inis
when"0000"=>show<="0111111";
when"0001"=>show<="0000110";
when"0010"=>show<="1011011";
when"0011"=>show<="1001111";
when"0100"=>show<="1100110";
when"0101"=>show<="1101101";
when"0110"=>show<="1111101";
when"0111"=>show<="0000111";
when"1000"=>show<="1111111";
when"1001"=>show<="1101111";
whenothers=>show<="1000110";
endcase;
endprocess;
endone;
------------------------------------------------------------------
--实验要求:
设计一个有效位为4位的十进制的数字频率计。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfcounteris
port(rst:
instd_logic;--异步复位低电平有?
clk0:
instd_logic;--频率时钟、动态扫描频率
clkf:
instd_logic;--待测时钟
led:
outstd_logic_vector(7downto0);--八段数码管
enled:
inoutstd_logic_vector(3downto0));--动态显示数码管使能〔静态显示无法控制小数点〕
constantN:
integer:
=512;--时钟的频率,单位Hz
endentity;
architecturebevoffcounteris
signalb1,b2,b3,b4,b5,b6,b7:
std_logic_vector(3downto0);
signalbcd:
std_logic_vector(3downto0);
signaldpoint:
integerrange0to4;
signalbcd0,bcd1,bcd2,bcd3:
std_logic_vector(3downto0);
signalenable,clkable:
std_logic;
signalcounter:
integerrange0to3*N;
begin
process(clk0,rst)
begin
ifrst='0'then
counter<=0;
enable<='0';
elsifclk0'eventandclk0='1'then
ifcountercounter<=counter+1;
enable<='1';
else
enable<='0';
endif;
endif;
endprocess;
process(clkf,enable)
begin
clkable<=clkfandenable;
endprocess;
process(clkable,rst)
begin
ifrst='0'then--复位或显示周期
b1<="0000";
b2<="0000";
b3<="0000";
b4<="0000";
b5<="0000";
b6<="0000";
b7<="0000";
elsifrising_edge(clkable)then--计数周期中
--各位按顺序如果小于9那么加1,等于9那么进位回0
ifb1="1001"then
b1<="0000";
ifb2="1001"then
b2<="0000";
ifb3="1001"then
b3<="0000";
ifb4="1001"then
b4<="0000";
ifb5="1001"then
b5<="0000";
ifb6="1001"then
b6<="0000";
ifb7="1001"then
b7<="0000";
else
b7<=b7+1;
endif;
else
b6<=b6+1;
endif;
else
b5<=b5+1;
endif;
else
b4<=b4+1;
endif;
else
b3<=b3+1;
endif;
else
b2<=b2+1;
endif;
else
b1<=b1+1;
endif;
endif;
endprocess;
process(b1,b2,b3,b4,b5,b6,b7)--控制显示位,并确定小数点位置
begin
--ifenable='0'then--显示周期
ifb7>"0000"then--10M>频率>=1M,超出10M无法正确显示
bcd3<=b7;bcd2<=b6;bcd1<=b5;bcd0<=b4;dpoint<=1;
elsifb6>"0000"then--1M>频率>=100K
bcd3<=b6;bcd2<=b5;bcd1<=b4;bcd0<=b3;dpoint<=2;
elsifb5>"0000"then--100K>频率>=10K
bcd3<=b5;bcd2<=b4;bcd1<=b3;bcd0<=b2;dpoint<=3;
else--10K>频率>=1K
bcd3<=b4;bcd2<=b3;bcd1<=b2;bcd0<=b1;dpoint<=4;
endif;
--endif;
endprocess;
process(clk0)--动态显示出频率和小数点
begin
ifrising_edge(clk0)then
caseenledis
when"0001"=>
bcd<=bcd1;
if(dpoint=2)then
led(0)<='1';
else
led(0)<='0';
endif;
enled<="0010";
when"0010"=>
bcd<=bcd2;
if(dpoint=3)then
led(0)<='1';
elseled(0)<='0';
endif;
enled<="0100";
when"0100"=>
bcd<=bcd3;
if(dpoint=4)then
led(0)<='1';
elseled(0)<='0';
end