基于QUASTUS II的波形信号发生器.docx
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基于QUASTUSII的波形信号发生器
正文
一、设计思路
1.基于QUASTUSII平台,利用DDS(直接数字信号合成)技术,采用VHDL语言,设计一波形信号发生器。
首先根据对各波形的幅度进行采样,获得各波形的波形数据表,然后FPGA根据输入的时钟(频率可根据要求可变)作为地址信号,从FPGA数据线上输出相应的波形数据,再送入实验板上的D/A转换芯片进行转换为模拟信号,最后送入滤波电路滤波后输出。
2.实验整体框图如下:
由斜降锯齿波模块(dj)、斜升锯齿波模块(dz)、方波模块(fb)、三角波模块(jcb)、阶梯波模块(jtb)、6选1选择器(xz)正弦波模块(zx)以及、译码显示模块(ym)组成。
二、设计输入文件与调试
1.分频器
用4个100分频器串接实现。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfenpinis
port(clk:
instd_logic;
clkfen:
outstd_logic);
endfenpin;
architecturefenpinoffenpinis
signalclk_mid:
std_logic;
begin
process(clk)
variabledata:
integerrange0to99;
begin
ifclk'eventandclk='1'then
ifdata=99then
data:
=0;
clk_mid<=notclk_mid;
else
data:
=data+1;
endif;
endif;
clkfen<=clk_mid;
endprocess;
endfenpin;
2.递减(锯齿波)波形数据产生模块设计
采用255~0循环加法计数器实现。
设计思路是:
reset是复位信号,要首先考虑。
tmp是引进的一个中间变量。
通过赋值给输出值。
clk是时钟信号,当复位信号有效时,输出为‘1’,输出最大值设为“255”,最小值设为“0”,从“0”开始,当时钟检测到有上升沿的时候,输出就会呈现递减的趋势,减“1”。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdjIS
PORT(clk,reset:
INSTD_LOGIC;
q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDdj;
ARCHITECTUREbehaveOFdjIS
BEGIN
PROCESS(clk,reset)
VARIABLEtmp:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
IFreset='0'THEN
tmp:
="11111111";
ELSIFclk'EVENTANDclk='1'THEN
IFtmp="00000000"THEN
Tmp:
="11111111";
ELSE
tmp:
=tmp-1;
ENDIF;
ENDIF;
q<=tmp;
ENDPROCESS;
ENDbehave;
3.递增(锯齿波)波形数据产生模块设计
采用0~255循环加法计数器实现。
与递减相反。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdzIS
PORT(clk,reset:
INSTD_LOGIC;
q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDdz;
ARCHITECTUREbehaveOFdzIS
BEGIN
PROCESS(clk,reset)
VARIABLEtmp:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
IFreset='0'THEN
tmp:
="00000000";
ELSIFclk'EVENTANDclk='1'THEN
IFtmp="11111111"THEN
tmp:
="00000000";
ELSE
tmp:
=tmp+1;
ENDIF;
ENDIF;
q<=tmp;
ENDPROCESS;
ENDbehave;
4.方波波形数据产生模块设计
采用高/低电平实现,用cnt来控制方波的周期,用a的值来控制输出到底是高电平还是低电平。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYfbIS
PORT(clk,reset:
INSTD_LOGIC;
q:
OUTINTEGERRANGE0TO255);
ENDfb;
ARCHITECTUREbehaveOFfbIS
SIGNALa:
BIT;
BEGIN
PROCESS(clk,reset)
VARIABLEcnt:
INTEGERrange0to31;
BEGIN
IFreset='0'THEN
A<='0';
ELSIFclk'EVENTANDclk='1'THEN
IFcnt<31THEN
Cnt:
=cnt+1;
ELSE
cnt:
=0;
a<=NOTa;
ENDIF;
ENDIF;
ENDPROCESS;
Process(clk,a)
BEGIN
IFclk'EVENTANDclk='1'THEN
IFa='1'THEN
Q<=255;
ELSE
Q<=0;
ENDIF;
ENDIF;
ENDPROCESS;
ENDbehave;
5.三角波波形数据产生模块设计
采用0~255~0循环加/减法计数器实现。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYjcbIS
PORT(clk,reset:
INSTD_LOGIC;
q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDjcb;
ARCHITECTUREbehaveOFjcbIS
BEGIN
PROCESS(clk,reset)
VARIABLEtmp:
STD_LOGIC_VECTOR(7DOWNTO0);
VARIABLEa:
STD_LOGIC;
BEGIN
IFreset='0'THEN
tmp:
="00000000";
ELSIFclk'EVENTANDclk='1'THEN
IFa='0'THEN
IFtmp="11111110"THEN
tmp:
="11111111";
a:
='1';
ELSE
tmp:
=tmp+1;
ENDIF;
ELSE
IFtmp="00000001"THEN
tmp:
="00000000";
a:
='0';
ELSE
tmp:
=tmp-1;
ENDIF;
ENDIF;
ENDIF;
q<=tmp;
ENDPROCESS;;
ENDbehave
6.阶梯波形数据产生模块设计
可采用八进制计数器实现,每次阶梯常数为32。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityjtbis
port(clk,reset:
instd_logic;
q:
outstd_logic_vector(7downto0));
endjtb;
architectureaofjtbis
begin
process(clk,reset)
variabletmp:
std_logic_vector(7downto0);
begin
ifreset='0'then
tmp:
="00000000";
elseifclk'eventandclk='1'then
iftmp="11111111"then
tmp:
="00000000";
else
tmp:
=tmp+16;
endif;
endif;
endif;
q<=tmp;
endprocess;
enda;
7.正弦波波形数据产生模块设计
采用描点法来描述正弦波,在仿真波形中可以看到输入输出引脚设置,其中clk输入时钟端口,reset为输入复位端口,d为整数输出端口,一个周期选取64个点,计算出64个常数后,查表输出[5]。
复位信号的级别高于其它信号,而且低电平是有效电平,所以整个程序的工作状态应处于高电平状态。
当时钟检测到上升沿时,计数器计数,描点工作开始。
没达到最大值之前,一直自加,否则就自动转为“0”。
那么首先要确定这64个点。
然后在程序里用case语句来择。
libraryieee;
useieee.std_logic_arith.all;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityzxis
port(clk:
instd_logic;
reset:
instd_logic;
q:
outstd_logic_vector(7downto0));
endzx;
architecturebehavofzxis
signalb:
integerrange0to63;
signald:
integerrange0to255;
begin
process(clk)
begin
ifreset='0'thenb<=0;
elsifclk'eventandclk='1'then
ifb=63thenb<=0;
elseb<=b+1;
endif;
endif;
endprocess;
process(b)
begin
casebis
when00=>d<=255;when01=>d<=254;when02=>d<=252;when03=>d<=249;
when04=>d<=245;when05=>d<=239;when06=>d<=233;when07=>d<=225;
when08=>d<=217;when09=>d<=207;when10=>d<=197;when11=>d<=186;
when12=>d<=174;when13=>d<=162;when14=>d<=150;when15=>d<=137;
when16=>d<=124;when17=>d<=112;
when18=>d<=99;when19=>d<=87;when20=>d<=75;when21=>d<=64;when22=>d<=53;when23=>d<=43;when24=>d<=34;when25=>d<=26;when26=>d<=19;when27=>d<=13;
when28=>d<=8;when29=>d<=4;
when30=>d<=1;when31=>d<=0;
when32=>d<=0;when33=>d<=1;
when34=>d<=4;when35=>d<=8;
when36=>d<=13;when37=>d<=19;when38=>d<=26;when39=>d<=34;
when40=>d<=43;when41=>d<=53;when42=>d<=64;when43=>d<=75;
when44=>d<=87;when45=>d<=99;when46=>d<=112;when47=>d<=124;
when48=>d<=137;when49=>d<=150;when50=>d<=162;when51=>d<=174;
when52=>d<=186;when53=>d<=197;when54=>d<=207;when55=>d<=217;
when56=>d<=225;when57=>d<=233;when58=>d<=239;when59=>d<=245;
when60=>d<=249;when61=>d<=252;when62=>d<=254;when63=>d<=255;
whenothers=>null;
endcase;
endprocess;
q<=conv_std_logic_vector(d,8);
endbehav;
8.六选一选择器模块设计
用CASE语句设计完成。
在CORTROL的控制下选择输出一种波形数据输出
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYxzIS
PORT(sel:
INSTD_LOGIC_VECTOR(2DOWNTO0);
d0,d1,d2,d3,d4,d5:
INSTD_LOGIC_VECTOR(7DOWNTO0);
q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDxz;
ARCHITECTUREbehaveOFxzIS
BEGIN
PROCESS(sel)
BEGIN
CASEselIS
WHEN"000"=>q<=d0;
WHEN"001"=>q<=d1;
WHEN"010"=>q<=d2;
WHEN"011"=>q<=d3;
WHEN"100"=>q<=d4;
WHEN"101"=>q<=d5;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDbehave;
9.译码
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
useieee.std_logic_unsigned.all;
entityymis
port(clk,rst:
instd_logic;
data:
instd_logic_vector(7downto0);
sel:
outstd_logic_vector(2downto0);
data_disp:
outstd_logic_vector(6downto0));
endym;
architectureRTLofymis
signalcount:
integerrange9downto0;
signaltemp:
integerrange4downto0;
signalnumber_h,number_t,number_l:
integerrange0to9;
begin
process(data,clk,rst)
begin
if(rst='0')then
number_h<=0;
number_t<=0;
number_l<=0;
elsif(to_integer(unsigned(data))>=200ANDto_integer(unsigned(data))-200>=50)then
number_h<=2;
number_t<=5;
number_l<=to_integer(unsigned(data))-250;
elsif(to_integer(unsigned(data))>=200ANDto_integer(unsigned(data))-200>=40)then
number_h<=2;
number_t<=4;
number_l<=to_integer(unsigned(data))-240;
elsif(to_integer(unsigned(data))>=200ANDto_integer(unsigned(data))-200>=30)then
number_h<=2;
number_t<=3;
number_l<=to_integer(unsigned(data))-230;
elsif(to_integer(unsigned(data))>=200ANDto_integer(unsigned(data))-200>=20)then
number_h<=2;
number_t<=2;
number_l<=to_integer(unsigned(data))-220;
elsif(to_integer(unsigned(data))>=200ANDto_integer(unsigned(data))-200>=10)then
number_h<=2;
number_t<=1;
number_l<=to_integer(unsigned(data))-210;
elsif(to_integer(unsigned(data))>=200)then
number_h<=2;
number_t<=0;
number_l<=to_integer(unsigned(data))-200;
elsif(to_integer(unsigned(data))>=100ANDto_integer(unsigned(data))-100>=90)then
number_h<=1;
number_t<=9;
number_l<=to_integer(unsigned(data))-
190;
elsif(to_integer(unsigned(data))>=100ANDto_integer(unsigned(data))-100>=80)then
number_h<=1;
number_t<=8;
number_l<=to_integer(unsigned(data))-180;
elsif(to_integer(unsigned(data))>=100ANDto_integer(unsigned(data))-100>=70)then
number_h<=1;
number_t<=7;
number_l<=to_integer(unsigned(data))-170;
elsif(to_integer(unsigned(data))>=100ANDto_integer(unsigned(data))-100>=60)then
number_h<=1;
number_t<=6;
number_l<=to_integer(unsigned(data))-160;
elsif(to_integer(unsigned(data))>=100ANDto_integer(unsigned(data))-100>=50)then
number_h<=1;
number_t<=5;
number_l<=to_integer(unsigned(data))-150;
elsif(to_integer(unsigned(data))>=100ANDto_integer(unsigned(data))-100>=40)then
number_h<=1;
number_t<=4;
number_l<=to_integer(unsigned(data))-
140;
elsif(to_integer(unsigned(data))>=100ANDto_integer(unsigned(data))-100>=30)then
number_h<=1;
number_t<=3;
number_l<=to_integer(unsigned(data))-130;
elsif(to_integer(unsigned(data))>=100ANDto_integer(unsigned(data))-100>=20)then
number_h<=1;
number_t<=2;
number_l<=to_integer(unsigned(data))-120;
elsif(to_integer(unsigned(data))>=100ANDto_integer(unsigned(data))-100>=10)then
number_h<=1;
number_t<=1;
number_l<=to_integer(unsigned(data))-110;
elsif(to_integer(unsigned(data))>=100)then
number_h<=1;
number_t<=0;
number_l<=to_integer(unsigned(data))-100;
elsif(to_integer(unsigned(data))>=90)then
number_h<=0;
number_t<=9;
number_l<=to_integer(unsigned(data))-90;
elsif(to_integer(unsigned(data))>=80)then
number_h<=0;
number_t<=8;
number_l<=to_integer(unsigned(data))-80;
elsif(to_integer(unsigned(data))>=70)then
number_h<=0;
number_t<=7;
number_l<=to_integer(unsigned(data))-70;
elsif(to_integer(unsigned(data))>=60)then
number_h<=0;
number_t<=6;
number_l<=to_integer(unsigned(data))-60;
elsif(to_integer(unsigned(data))>=50)then
number_h<=0;
number_t<=5;
number_l<=to_integer(unsigned(data))-50;
elsif(to_integer(unsigned(data))>=40)then
number_