外文文献翻译 基于单片机的频率计设计本科学位论文.docx

外文文献翻译 基于单片机的频率计设计本科学位论文.docx

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外文文献翻译基于单片机的频率计设计本科学位论文

原文：

ThisdesigntakeatMCS-51monolithicintegratedcircuitasthecorefullusehardwaresourcedesign'sonekindoffrequencymeter,thisfrequencymeterwillbemeasuredfirstthatsignalenlargementreshapingprocessing,turnssatisfiesTTL/whichthemonolithicintegratedcircuitI/OmouthacceptstheCMOScompatiblesignalfrommonolithicintegratedcircuit'sT1inputportinputdirectsummationpulsenumber,themonolithicintegratedcircuitinteriortimerfixedtimeis1S,bynowaccumulatedthepulsenumbernamelyforismeasuredthesignalthefrequency.Finallypassesthroughmonolithicintegratedcircuitprocessingtodelivertothelcdliquidcrystaldisplaymonitordemonstration.

CentralProcessingUnitDesigns

TheCPUisthekeycomponentofadigitalcomputer.Itspurposeistodecodeinstructionreceivedfrommemoryandperformtransfers,arithmetic,logic,andcontroloperationswithdatastoredininternalregisters,memory,orI/Ointerfaceunits.Externally,theCPUprovidesoneormorebusesfortransferringinstructions,data,andcontrolinformationtoandfromcomponentsconnectedtoit.Inthegenericcomputeratthebeginningofchapter1,theCPUisapartoftheprocessorandisheavilyshaded.CPUs,however,mayalsoappearincomputers.Small,relativelysimplecomputerscalledmicrocontrollersareusedincomputersandinotherdigitalsystemstoperformlimitedorspecializedtasks.Forexample,amicrocontrollerispresentinthekeyboardandinthemonitorinthegenericcomputer;thus,thesecomponentsarealsoshaded.Insuchmicrocontrollers,theCPUmaybequitedifferentfromthosediscussedinthischapter.Thewordlengthsmaybeshort（say,fouroreightbits）,thenumberofregisterssmall,andtheinstructionsetslimited.Performance,relativelyspeaking,ispoor,butadequateforthetask.Mostimportant,thecostofthesemicrocontrollersisverylow,makingtheirusecosteffective.

Inthefollowingpages,weconsidertwocomputerCPUs,oneforacomplexinstructionsetcomputer（CISC）andtheotherforareducedinstructionsetcomputer（RISC）.Afteradetailedexaminationofthedesigns,wecomparetheperformanceofthetwoCPUsandpresentabriefoverviewofsomemethodsusedtoenhancethatperformance.Finally,werelatethedesignideasdiscussedtogeneraldigitalsystemdesign.

1、Thecomplexinstructionsetcomputer

Thefirstdesignwepresentisforacomplexinstructionsetcomputerwithanon-pipelineddatapathandmicroprogrammedcontrolunit.Webeginbydescribingtheinstructionsetarchitecture,includingtheCPUregisterset,instructionformats,andaddressingmodes.TheCISCnatureoftheinstructionsetarchitectureisdemonstratedbyitsmemory-to-memoryaccessfordatamanipulationinstructions,eightaddressingmodes,twoinstructionformatlengths,andinstructionsthatrequiresignificantsequencesofoperationsfortheirexecution.

WedesignadatapathforimplementingtheCISCarchitecture.ThedatapathisbasedontheoneinitiallydescribedinSection7-9andincorporatedintoaCPUinsection8-10.modificationsaremadetotheregisterfile,thefunctionunit,andthebusestosupportthepresentinstructionsetarchitecture.

Oncethedatapathhasbeenspecified,acontrolunitisdesignedtocompletetheimplementationoftheinstructionsetarchitecture.Thedesignofthecontrolunitmustinvolveacoordinateddefinitionofboththehardwareorganizationandthemicroprogramorganization.Inparticular,dividingthemicroprogramintomicroroutines,whileatthesametimedesigningthesequencerwithwhichtheyinteract,isakeypartofthedesign.Eventheinstructionfieldsandopposedaretiedtothiscoordinatedeffort.Followingthedefinitionofthehardwareandmicrocodeorganizations,wedetailessentialpartsofthemicrocodeandthemicroroutinesforrepresentativeoperations.

Instructionsetarchitecture

Figure10-1showstheCISCregistersetaccessibletotheprogrammer.Allregistershave16bits.Theregisterfilehaseightregisters,R0thoughR7.R0isaspecialregisterthatalwayssuppliesthevaluezerowhenitisusedasasourceanddiscardstheresultwhenitisusedasadestination.

Inadditionaltotheregisterfile,thereisaprogramcounterPCandstackpointerSP.Thepresenceofastackpointerindicatesthatamemorystackisapartofthearchitecture.thefinalregisteristheprocessorstatusregisterPSR,whichcontainsinformationonlyinitsrightmostthefivebits;theremainderoftheregisterisassumedtocontainzero.ThePSRcontainsthefourstoredstatusbitvaluesZ,N,C,andVinpositions3through0,respectively.Inadditional,astoredinterruptenablebitEIappearsinposition4.

Table10-1containsthe42operationsperformedbytheinstructions.Eachoperationhasamnemonicandacarefullyselectedoppose.Theoperationsaredividedintofourgroupsbasedonthenumberofexplicitoperandsandwhethertheoperationisbranch.Inaddition,thestatusbitsaffectedbytheoperationarelisted.

Figure10-2givestheinstructionformatsfortheCPU.Thegenericinstructionformathasfivefields.Thefirst,OPCODE,specifiesoftheoperation.Thenexttwo,MODEandS,areusedtodeterminetheaddressesoftheoperands.Thelasttwofields,SRCandDST,arethe3-bitsourceregisteranddestinationregisteraddressfields,respectively.Inaddition,thereisanoptionalsecondwordWthatappearswithsomeinstructionsasanoperandoranaddress,butnotwithothers.

ThefirsttwobitsofOPCODE,IR（15:

14）,determinethenumberofexplicitoperandsandhowthefieldsoftheformatareused.Whenthesebitsare00,eithernooperandisrequiredorthelocationoftheoperandisimpliedbyOPCODE.OnlytheOPCODEfieldisneeded,asshowninfigure2（b）.thefourrightmostOPCODEbitscanspecifyupto16operandsorwithimpliedoperandaddresses.

IfIR（15:

14）is01,theinstructionhasoneoperandandisadatatransferordatamanipulationinstruction.Sincethereisanoperand,theMODEfieldspecifiestheaddressingmodeforobtainingit.ThesingleaddressmayinvolvetheDSTregisteraddressinitsformation,sotheDSTfieldisalsopresent.TheSfieldandSRCfieldrelatetothepresenceoftwooperandsandsoarenotusedforthetypicalsingleoperandinstructions.but,theshiftinstructionsrequireashiftamounttoindicatehowmanybitstoshift.Formaximumflexibility,thisshiftamountistreatedjustlikeasourceoperand.Asaconsequence,theSHAandSfieldsisafull16-bitoperand,butonlyvalues0through15aremeaningful.TherearesufficientOPCODEbitsfor16instructionswithasingleoperand.

Table10-2givestheaddressingmodesspecifiedbytheMODEfield.ThefirsttwobitsofMODEspecifyfourdifferenttypesofaddressing:

register,immediate,indexed,andrelativetothePC.ThethirdbitofMODEspecifieswhethertheaddressgeneratedbythesemodesisusedasanindirectaddress.Theoneexceptiontothisisdirectaddressing,whichisobtainedbyapplyingindirectiontotheimmediatetype.Otherwise,ifthethirdbitequals0,indirectaddressingdoesnotapplywhereas,ifitequals1,indirectaddressingdoesapply.Fortheregistertypeofinstruction,MONE（2:

1）=00andtheWwordisnotneeded.Sincetheoperandoraddresscomesfromaregister.Thethirdcolumnofthetableprovidesregistertransferstatementsforeachoftheaddressingmodesfortheone-operandinstructions.

IfIR（15:

14）isequalto10,thentheinstructionhastwoaddressesusedfortrueoperands.Allfieldsofthegenericinstruction,includingSandSRC,areusedforthiscaseforallinstructions.oneofaddresses,eitherthesourceorthedestination,usestheaddressingmodes.IfS=0,thenthesourceusestheaddressingmodespecifiedbyMODE,andthesourceisaregister.IfS=1,thenthedestinationusestheaddressingmode,andthesourceisaregister.RegistertransferdescriptionsoftheresultingaddressesaregiveninthefourthandfifthcolumnsofTable2.Again,dependingonthecontentsoftheMODEfield,thesecondinstructionwordW,whichisanaddressoranimmediateoperand,mayormaynotbepresent.

InstructionswithIR（15:

14）=11arebranches.AsideformtheSfieldandtheSHAfieldforshifts,theformatisthesameasforIR（15:

14）=01.Forallinstructionsofthistype,thedestinationaddress（nottheoperand）becomesthenewaddressplacedintheprogramcounterPC.Asaconsequence,theregistermodeisinvalidforbranchinstructions.

Beforeproceedingtothenextstep,whichdefinesthedatapathtosupporttheinstructionsetarchitecture,wewillbrieflynotethecharacteristicsofthearchitecturethatdefineitasCISCorRISC.MostoftheoperationsgiveninChapter9areincludedintheinstructionset.Anumberofoperationsthatdonotappearareredundant.Thesameactionscanbeachievedbyusingproperaddressingmodeswithinstructionsthatdoappear.Forexample,LD,ST,IN,andOUTcanallbeachievedbyusingMOVEinstructionsinamemory-mappedstructure.Bylookingattheformatsfortheinstructions,wefindthatmostoftheinstructionscanoperatedirectlyonoperatedirectlyonoperandsfrommemory.Thereareeightaddressingmodesandtwodifferentlengthsofinstructionformats.Inaddition,someoftheinstructionsperformcomplexoperationswhichcanbeviewedasoperationsthatarelikelytotakemorethanoneclockcyclefortheexecutionstep.ThesecharacteristicsclearlyidentifythisasaCISCarchitecture.

Datapathorganization

Ratherthanbeginningfromscratch,wewillreusethenon-pipelineddatapathemployedwiththemicroprogrammedcontrolinsection8-10,withmodifications.Thatdatapathwasshowninsection8-10,andthenew,modifieddatap