基于VHDL万年历的设计.docx
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基于VHDL万年历的设计
数字万年历与数字钟的设计
一、设计要求
数字万年历要求可以任意设定年份月份和日期；当当日时钟走过24时（即0点）后，日期能够自动改变。
同样，当每月的最后一天走完后，月份也能够自动显示为下一个月。
年份的变化也是如此。
时钟计时按照一天24小时计。
时钟也可以按照由人工设定当前时间，或者修改当前时间，修改完成后，计时即有当前时间开始。
显示方式：
日期为2001-11-08，时钟为hh-mm-ss；日期和时钟轮流显示。
二、设计原理
本设计先用VHDL语言写出需要的各个小模块，并将这些模块进行编译并打包成图形文件，最后将这些图形文件在顶层文件里进行连线，实现具体要求与功能。
实验源程序：
LIBRARYIEEE;
USEIEEE.std_logic_1164.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
USEIEEE.std_logic_unsigned.ALL;
ENTITYonesecondIS
PORT（
RESET:
INSTD_LOGIC;
GCLKP1:
INSTD_LOGIC;
clkout:
outstd_logic
）;
ENDonesecond;
ARCHITECTUREFrequency_archOFonesecondIS
SIGNALPeriod1S:
STD_LOGIC;
BEGIN
PROCESS（RESET,GCLKP1）
VARIABLECount1:
STD_LOGIC_VECTOR（25DOWNTO0）;
BEGIN
IF（GCLKP1'EVENTANDGCLKP1='1'）THEN
IF（Count1>"10111110101111000010000000"）THEN
Count1:
="00000000000000000000000000";
ELSE
Count1:
=Count1+1;
ENDIF;
Period1S<=Count1（25）;--1MHz
ENDIF;
clkout<=Period1S;
endprocess;
ENDFrequency_arch;
60进制
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt60is
port（
clk:
instd_logic;
ld:
instd_logic;
da,db:
instd_logic_vector（3downto0）;
outa:
outstd_logic_vector（3downto0）;
outb:
outstd_logic_vector（3downto0）;
c0:
outstd_logic
）;
endcnt60;
architectureoneofcnt60is
signalma,mb:
std_logic_vector（3downto0）;
begin
c0<='1'WHEN（ma=5andmb=9）else'0';
process（clk,ld）
begin
ifclk'eventandclk='1'then
ifld='1'then
ma<=da;
mb<=db;
elsifma=5andmb=9then
mb<="0000";
ma<="0000";
elsifmb=9then
mb<="0000";
ma<=ma+1;
elsemb<=mb+1;
endif;
endif;
endprocess;
outa<=ma;
outb<=mb;
endone;
24进制程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt24is
port（clk:
instd_logic;
ld:
instd_logic;
da,db:
instd_logic_vector（3downto0）;
outa:
outstd_logic_vector（3downto0）;
outb:
outstd_logic_vector（3downto0）;
c0:
outstd_logic
）;
endcnt24;
architectureoneofcnt24is
signalma,mb:
std_logic_vector（3downto0）;
begin
c0<='1'WHEN（ma=2andmb=3）else'0';
process（clk,ld）
begin
ifclk'eventandclk='1'then
ifld='1'thenma<=da;mb<=db;
elsifma=2andmb=3then
mb<="0000";
ma<="0000";
elsifmb=9
then
mb<="0000";
ma<=ma+1;
else
mb<=mb+1;
endif;
endif;
endprocess;
outa<=ma;
outb<=mb;
endone;
天
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydayis
port（
clk:
instd_logic;
ld:
instd_logic;
maxday:
instd_logic_vector（1downto0）;
da:
instd_logic_vector（3downto0）;
db:
instd_logic_vector（3downto0）;
outa:
outstd_logic_vector（3downto0）;
outb:
outstd_logic_vector（3downto0）;
c0:
outstd_logic
）;
endday;
architectureoneofdayis
signalma:
std_logic_vector（3downto0）;
signalmb:
std_logic_vector（3downto0）;
begin
process（clk,ld）
begin
ifclk'eventandclk='1'then
ifld='1'thenma<=da;mb<=db;
casemaxdayis
when"00"=>--28
if（ma=2andmb=8）thenma<="0000";mb<="0001";c0<='1';
elseifmb=9thenmb<="0000";ma<=ma+1;c0<='0';
elsemb<=mb+1;c0<='0';
endif;
endif;
when"01"=>--29
if（ma=2andmb=9）thenma<="0000";mb<="0001";c0<='1';
elseifmb=9thenmb<="0000";ma<=ma+1;c0<='0';
elsemb<=mb+1;c0<='0';
endif;
endif;
when"10"=>--30
if（ma=3andmb=0）thenma<="0000";mb<="0001";c0<='1';
elseifmb=9thenmb<="0000";ma<=ma+1;c0<='0';
elsemb<=mb+1;c0<='0';
endif;
endif;
whenothers=>--31
if（ma=3andmb=1）thenma<="0000";mb<="0001";c0<='1';
elseifmb=9thenmb<="0000";ma<=ma+1;c0<='0';
elsemb<=mb+1;c0<='0';
endif;
endif;
endcase;
endif;
endif;
endprocess;
outa<=ma;
outb<=mb;
endone;
月
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyueis
port（
clk,ld:
instd_logic;
da:
instd_logic_vector（3downto0）;
db:
instd_logic_vector（3downto0）;
runnian:
instd_logic;
outa:
outstd_logic_vector（3downto0）;
outb:
outstd_logic_vector（3downto0）;
c0:
outstd_logic;
maxday:
outstd_logic_vector（1downto0）
）;
endyue;
architectureoneofyueis
signalmb:
std_logic_vector（3downto0）;
signalma:
std_logic_vector（3downto0）;
begin
process（clk,ld）
begin
if（clk'eventandclk='1'）then
ifld='1'then
ma<=da;mb<=db;
if（ma=1andmb=2）then
ma<="0000";
mb<="0001";
elsifmb=9then
mb<="0000";
ma<=ma+1;
else
mb<=mb+1;
endif;
endif;
endif;
endprocess;
outa<=ma;
outb<=mb;
c0<='1'WHEN（ma=1andmb=2）else'0';
maxday<="00"whenma=0andmb=2andrunnian='0'else
"01"whenma=0andmb=2andrunnian='1'else
"10"when（ma=0andmb=4）or（ma=0andmb=6）or（ma=0andmb=9）or（ma=1andmb=1）else
"11";
endone;
年
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitynianis
port（
ld1,ld2,clk:
instd_logic;
dy1,dy2:
instd_logic_vector（3downto0）;
y1,y2,y3,y4:
outstd_logic_vector（3downto0）;
run,cout:
outstd_logic）;
endnian;
architectureoneofnianis
signalq1,q2,q3,q4:
std_logic_vector（3downto0）;
signalsum,sum1,sum2:
std_logic_vector（1downto0）;
begin
process（clk,ld1,ld2）
begin
ifclk'eventandclk='1'then
ifld1='1'then
q1<=dy1;
q2<=dy2;
elsifld2='1'then
q3<=dy1;
q4<=dy2;
else
q1<=q1+1;
ifq1=9then
q1<=（others=>'0'）;
q2<=q2+1;
endif;
ifq1=9andq2=9then
q1<=（others=>'0'）;
q2<=（others=>'0'）;
q3<=q3+1;
endif;
ifq1=9andq2=9andq3=9then
q1<=（others=>'0'）;
q2<=（others=>'0'）;
q3<=（others=>'0'）;
q4<=q4+1;
endif;
ifq2=9andq1=9andq3=9andq4=9then
q4<="0000";
q3<="0000";
q2<="0000";
q1<="0000";
cout<='1';
elsecout<='0';
endif;
endif;
endif;
endprocess;
withconv_integer（q4）select
sum1<="10"when1|3|5|7|9,
"00"whenothers;
withconv_integer（q2）select
sum2<="10"when1|3|5|7|9,
"00"whenothers;
process（q1,q2,q3,q4,sum1,sum2）
begin
if（q1="0000"andq2="0000"）then
sum<=sum1+q3（1downto0）;
else
sum<=sum2+q1（1downto0）;
endif;
endprocess;
run<='1'whensum="00"else'0';
y1<=q1;
y2<=q2;
y3<=q3;
y4<=q4;
endone;
置数选择程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityyima1is
port（
x:
instd_logic_vector（2downto0）;
y0,y1,y2,y3,y4,y5,y6,y7:
outstd_logic）;
endyima1;
architectureaofyima1is
signalda:
std_logic_vector（7downto0）;
begin
withxselect
da<="00000001"when"000",
"00000010"when"001",
"00000100"when"010",
"00001000"when"011",
"00010000"when"100",
"00100000"when"101",
"01000000"when"110",
"10000000"when"111",
"00000000"whenothers;
y0<=da（0）;
y1<=da
（1）;
y2<=da
（2）;
y3<=da（3）;
y4<=da（4）;
y5<=da（5）;
y6<=da（6）;
y7<=da（7）;
enda;
显示
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydisplayis
port（
clk:
instd_logic;
c4:
instd_logic;
ya,yb,yc,yd,ma,mb,da,db,ha,hb,fa,fb,oa,ob:
instd_logic_vector（3downto0）;
d0,d1,d2,d3,d4,d5,d6,d7:
outstd_logic_vector（0to6）
）;
enddisplay;
architectureoneofdisplayis
signalw:
std_logic;
signals0,s1,s2,s3,s4,s5,s6,s7:
std_logic_vector（3downto0）;
begin
process（clk,c4）
begin
ifclk'eventandclk='1'then
casec4is
when'1'=>w<='0';--displayhourfenminute
when'0'=>w<='1';--displayyearmonthday
whenothers=>null;
endcase;
endif;
endprocess;
process（clk,w,ya,yb,yc,yd,ma,mb,da,db,ha,hb,fa,fb,oa,ob）
begin
ifclk'eventandclk='1'then
casewis
when'0'=>s0<=hb;s1<=ha;s2<="1111";s3<=fa;s4<=fb;s5<="1111";s6<=oa;s7<=ob;
whenothers=>s0<=ya;s1<=yb;s2<=yc;s3<=yd;s4<=ma;s5<=mb;s6<=da;s7<=db;
endcase;
endif;
endprocess;
withs0select
d0<="0110000"when"0001",
"1101101"when"0010",
"1111001"when"0011",
"0110011"when"0100",
"1011011"when"0101",
"1011111"when"0110",
"1110000"when"0111",
"1111111"when"1000",
"1111011"when"1001",
"1111110"whenothers;
withs1select
d1<="0110000"when"0001",
"1101101"when"0010",
"1111001"when"0011",
"0110011"when"0100",
"1011011"when"0101",
"1011111"when"0110",
"1110000"when"0111",
"1111111"when"1000",
"1111011"when"1001",
"1111110"whenothers;
withs2select
d2<="0110000"when"0001",
"1101101"when"0010",
"1111001"when"0011",
"0110011"when"0100",
"1011011"when"0101",
"1011111"when"0110",
"1110000"when"0111",
"1111111"when"1000",
"1111011"when"1001",
"0000001"when"1111",
"1111110"whenothers;
withs3select
d3<="0110000"when"0001",
"1101101"when"0010",
"1111001"when"0011",
"0110011"when"0100",
"1011011"when"0101",
"1011111"when"0110",
"1110000"when"0111",
"1111111"when"1000",
"1111011"when"1001",
"1111110"whenothers;
withs4select
d4<="0110000"when"0001",
"1101101"when"0010",
"1111001"when"0011",
"0110011"when"0100",
"1011011"when"0101",
"1011111"when"0110",
"1110000"when"0111",
"1111111"when"1000",
"1111011"when"1001",
"1111110"whenothers;
withs5select
d5<="0110000"when"0001",
"1101101"when"0010",
"1111001"when"0011",
"0110011"when"0100",
"1011011"when"0101",
"1011111"when"0110",
"1110000"when"0111",
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