Verilog数字钟设计代码.docx
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Verilog数字钟设计代码
数字钟
一、简介
此数字钟为时分秒可调,带有闹钟设置。
各引脚功能入下:
clk:
输入时钟信号,为50mhz;(clk1k:
产生闹铃音、报时音的时钟信号,)
mode:
功能控制信号;为0:
计时功能;为1:
闹钟功能;为2:
手动校时功能;
turn:
接按键,在手动校时功能时,选择是调整小时,还是分钟;假如长时间按住该键,还可使秒信号清零,用于准确调时;
change:
接按键,手动调整时,每按一次,计数器加1;如果长按,如此连续快速加1,用于快速调时和定时;seg:
此信号分别输出显示数据;采用BCD码计数,分别驱动6个数码管显示时间;
scan:
数码管位选择信号输出
alert:
输出到扬声器的信号,用于产生闹铃音和报时音;闹铃音为持续20秒的急促的“嘀嘀嘀〞音,假如按住“change〞键,如此可屏蔽该音;整点报时音为“嘀嘀嘀嘀—嘟〞四短一长音;
LD_alert:
接发光二极管,指示是否设置了闹钟功能;
LD_hour:
接发光二极管,指示当前调整的是小时信号;
LD_min:
接发光二极管,指示当前调整的是分钟信号。
二、程序如下
moduleshuzizhong(clk,mode,change,turn,alert,seg,scan,LD_alert,LD_hour,LD_min);
inputclk,mode,change,turn;
outputalert,LD_alert,LD_hour,LD_min;
output[7:
0]scan,seg;
reg[7:
0]scan,seg;
reg[7:
0]hour,min,sec,hour1,min1,sec1,ahour,amin;
reg[1:
0]m,fm,num1,num2,num3,num4;
reg[1:
0]loop1,loop2,loop3,loop4,sound;
regLD_hour,LD_min;
regclk1hz,clk4hz,clk2hz,clk1khz,minclk,hclk;
regalert1,alert2,ear;
regcount1,count2,counta,countb;
reg[3:
0]data;
reg[2:
0]t8;
reg[14:
0]count3;
reg[6:
0]count4;
wirect1,ct2,cta,ctb,m_clk,h_clk;
//-------------------1khz,2hz--,1hz------------------------------------
always(posedgeclk)
begin
if(count3=='d25000)
beginclk1khz<=~clk1khz;count3<=0;
end
else
begincount3<=count3+1'b1;
end
end
always(posedgeclk1khz)//4hz
begin
if(count4=='d125)
beginclk4hz<=~clk4hz;count4<=0;
end
else
begincount4<=count4+1'b1;
end
end
always(posedgeclk4hz)//2hz
begin
clk2hz<=~clk2hz;
end
always(posedgeclk2hz)//1hz
begin
clk1hz<=~clk1hz;
end
//-----------------------------------------------------------
always(posedgeclk4hz)
begin
if(sound==3)
beginsound<=0;ear<=1;
end
else
beginsound<=sound+1'b1;ear<=0;
end
end
always(negedgemode)
begin
if(m==2)m<=0;
elsem<=m+1'b1;
end
always(negedgeturn)
begin
fm<=~fm;
end
//----------------------------------------------------------------
always
begin
case(m)
2:
beginif(fm)
begincount1<=change;{LD_min,LD_hour}<=2;end
else
begincounta<=change;{LD_min,LD_hour}<=1;end
{count2,countb}<=2'b11;
end
1:
beginif(fm)
begincount2<=change;{LD_min,LD_hour}<=2;end
elsebegincountb<=change;{LD_min,LD_hour}<=1;end
{count1,counta}<=2'b11;
end
default:
{count1,count2,counta,countb,LD_min,LD_hour}<=6'b111111;
endcase
end
always(negedgeclk4hz)
begin
if(!
count2)
begin
if(loop1==3)num1<=1;
else
beginloop1<=loop1+1'b1;num1<=0;
end
end
else
beginloop1<=0;num1<=0;
end
end
always(negedgeclk4hz)
begin
if(!
countb)
begin
if(loop2==3)num2<=1;
else
beginloop2<=loop2+1'b1;num2<=0;
end
end
else
beginloop2<=0;num2<=0;
end
end
always(negedgeclk4hz)
begin
if(!
count1)
begin
if(loop3==3)num3<=1;
else
beginloop3<=loop3+1'b1;num3<=0;
end
end
else
beginloop3<=0;num3<=0;
end
end
always(negedgeclk4hz)
begin
if(!
counta)
begin
if(loop4==3)num4<=1;
else
beginloop4<=loop4+1'b1;num4<=0;
end
end
else
beginloop4<=0;num4<=0;
end
end
assignct1=(num3&clk)|(!
num3&m_clk);
assignct2=(num1&clk)|(!
num1&(!
count2));
assigncta=(num4&clk)|(!
num4&h_clk);
assignctb=(num2&clk)|(!
num2&(!
countb));
//-----------------------------------------------------------------------------
always(posedgeclk1hz)
begin
if(!
(sec1^8'h59)|(!
turn)&(!
m))
beginsec1<=0;
if(!
((!
turn)&(!
m)))
minclk<=1;
end
else
begin
if(sec1[3:
0]==4'b1001)
beginsec1[3:
0]<=4'b0000;sec1[7:
4]<=sec1[7:
4]+1'b1;
end
elsesec1[3:
0]<=sec1[3:
0]+1'b1;minclk<=0;
end
end
assignm_clk=minclk||(!
count1);
always(posedgect1)
begin
if(min1==8'h59)
beginmin1<=0;hclk<=1;
end
else
begin
if(min1[3:
0]==9)
beginmin1[3:
0]<=0;min1[7:
4]<=min1[7:
4]+1'b1;
end
elsemin1[3:
0]<=min1[3:
0]+1'b1;hclk<=0;
end
end
assignh_clk=hclk||(!
counta);
always(posedgecta)//Сʱ¼ÆʱºÍСʱµ÷Õû½ø³Ì
if(hour1==8'h23)hour1<=0;
else
if(hour1[3:
0]==9)
beginhour1[7:
4]<=hour1[7:
4]+1'b1;hour1[3:
0]<=0;
end
elsehour1[3:
0]<=hour1[3:
0]+1'b1;
always(posedgect2)
if(amin==8'h59)amin<=0;
else
if(amin[3:
0]==9)
beginamin[3:
0]<=0;amin[7:
4]<=amin[7:
4]+1'b1;
end
elseamin[3:
0]<=amin[3:
0]+1'b1;
always(posedgectb)
if(ahour==8'h23)ahour<=0;
elseif(ahour[3:
0]==9)
beginahour[3:
0]<=0;ahour[7:
4]<=ahour[7:
4]+1'b1;
end
elseahour[3:
0]<=ahour[3:
0]+1'b1;
//---------------------------------------------------------------------------
always
if((min1==amin)&&(hour1==ahour)&&(amin|ahour)&&(change))
if(sec1<8'h20)alert1<=1;
elsealert1<=0;
elsealert1<=0;
always
begin
case(m)
3'b00:
beginhour<=hour1;min<=min1;sec<=sec1;end
3'b01:
beginhour<=ahour;min<=amin;sec<=8'bx;end
3'b10:
beginhour<=hour1;min<=min1;sec<=8'bx;end
default:
beginhour<=8'bx;min<=8'bx;sec<=8'bx;end
endcase
end
assignLD_alert=(ahour|amin)?
1'b1:
1'b0;
assignalert=((alert1)?
clk1khz&clk4hz:
1'b0)|alert2;
always
begin
if((min1==8'h59)&&(sec1>8'h54)||(!
(min1|sec1)))
if(sec1>8'h54)alert2<=ear&clk1khz;
elsealert2<=!
ear&clk1khz;
elsealert2<=0;
end
//-------------------------------------------------------------
always(posedgeclk1khz)
begin
t8<=t8+1'b1;
end
always
begin
case(t8[2:
0])
3'b000:
beginscan<=8'b01111111;data[3:
0]<=hour[7:
4];end
3'b001:
beginscan<=8'b10111111;data[3:
0]<=hour[3:
0];end
3'b010:
beginscan<=8'b11011111;data[3:
0]<=min[7:
4];end
3'b011:
beginscan<=8'b11101111;data[3:
0]<=min[3:
0];end
3'b100:
beginscan<=8'b11110111;data[3:
0]<=sec[7:
4];end
3'b101:
beginscan<=8'b11111011;data[3:
0]<=sec[3:
0];end
//3'b110:
beginscan<='b11111101;data[3:
0]<=4'b1011;end
//3'b111:
beginscan<='b11111110;data[3:
0]<=4'b1010;end
default:
beginscan<=8'b11111111;data[3:
0]<=4'bx;end
endcase
case(data[3:
0])
4'b0000:
seg[7:
0]<=8'b11000000;
4'b0001:
seg[7:
0]<=8'b11111001;
4'b0010:
seg[7:
0]<=8'b10100100;
4'b0011:
seg[7:
0]<=8'b10110000;
4'b0100:
seg[7:
0]<=8'b10011001;
4'b0101:
seg[7:
0]<=8'b10010010;
4'b0110:
seg[7:
0]<=8'b10000010;
4'b0111:
seg[7:
0]<=8'b11111000;
4'b1000:
seg[7:
0]<=8'b10000000;
4'b1001:
seg[7:
0]<=8'b10010000;
4'b1010:
seg[7:
0]<=8'b10001000;
4'b1011:
seg[7:
0]<=8'b10000011;
4'b1100:
seg[7:
0]<=8'b11000110;
4'b1101:
seg[7:
0]<=8'b10100001;
4'b1110:
seg[7:
0]<=8'b10000110;
4'b1111:
seg[7:
0]<=8'b10001110;
default:
seg[7:
0]<=8'bx;
endcase
end
endmodule
三、框图