VHDL参考资料.docx

VHDL参考资料.docx

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VHDL参考资料

VHDL快速参考手册

PRIMARYDESIGNUNITMODELSTRUCTURE

Each VHDLdesignunitcomprisesan"entity"declarationandoneormore"architectures".Eacharchitecturedefinesadifferentimplementationormodelofagivendesignunit.Theentitydefinitiondefinestheinputsto,andoutputsfromthemodule,andany"generic"parametersusedbythedifferentimplementationsofthemodule.

EntityDeclarationFormat

   entity name is

       port（portdefinitionlist）;--input/outputsignalports

       generic（genericlist）;  --optionalgenericlist

   endname;

Portdeclarationformat:

port_name:

modedata_type;

Themodeofaportdefinesthedirectionsofthesingalsonthatpirt,andisoneof:

in,out,buffer,orinout.

PortModes:

Aninport

canbereadbutnotupdatedwithinthemodule,carryinginformationintothemodule.（Aninportcannotappearonthelefthandsideofasignalassignment.）

Anoutport

canbeupdatedbutnotreadwithinthemodule,carryinginformationoutofthemodule.（Anoutportcannotappearontherighthandsideofasignalassigment.）

Abufferport

likewisecarriesinformationoutofamodule,butcanbebothupdatedandreadwithinthemodule.

Aninoutport

isbidirectionalandcanbebothreadandupdated,withmultipleupdatesourcespossible.

NOTE:

Abufferisstrictlyanoutputport,i.e.canonlybedrivenfromwithinthemodule,whileinoutistrulybidirectionalwithdriversbothwithinandexternaltothemodule.

Example

  entitycounteris

       port（Incr,Load,Clock:

in    bit;

             Carry:

            out   bit;

             Data_Out:

         bufferbit_vector（7downto0）;

             Data_In:

          in    bit_vector（7downto0））;

  endcounter;

Genericsallowstaticinformationtobecommunicatedtoablockfromitsenvironmentforallarchitecturesofadesignunit.Theseincludetiminginformation（setup,hold,delaytimes）,partsizes,andotherparameters.

Example

   entityand_gateis

       port（a,b:

in bit;

            c:

  outbit）;

       generic（gate_delay:

time:

=5ns）;

   endand_gate;

Architecture

Anarchitecturedefinesoneparticularimplementationofadesignunit,atsomedesiredlevelofabstraction.

 architecturearch_nameofentity_nameis

      ... declarations...

  begin

      ... concurrentstatements ...

  end

Declarationsincludedatatypes,constants,signals,files,components,attributes,subprograms,andotherinformationtobeusedintheimplementationdescription.Concurrentstatementsdescribeadesignunitatoneormorelevelsofmodelingabstraction,includingdataflow,structure,and/orbehavior.

∙BehavioralModel:

Nostructureortechnologyimplied.Usuallywritteninsequential,proceduralstyle.

∙DataflowModel:

Alldatapathsshown,plusallcontrolsignals.

∙StructuralModel:

Interconnectionofcomponents.

VHDLPACKAGES

AVHDLpackagecontainssubprograms,constantdefinitions,and/ortypedefinitionstobeusedthroughoutoneormoredesignunits.Eachpackagecomprisesa"declarationsection",inwhichtheavailable（i.e.exportable）subprograms,constants,andtypesaredeclared,anda"packagebody",inwhichthesubprogramimplementationsaredefined,alongwithanyinternally-usedconstantsandtypes.Thedeclarationsectionrepresentstheportionofthepackagethatis"visible"totheuserofthatpackage.Theactualimplementationsofsubroutinesinthepackagearetypicallynotofinteresttotheusersofthosesubroutines.

Packagedeclarationformat:

  packagepackage_nameis

    ...exportedconstantdeclarations

    ...exportedtypedeclarations

    ...exportedsubprogramdeclarations

  endpackage_name;

Example:

   packageee530is

      constantmaxint:

integer:

=16#ffff#;

      typearith_mode_typeis（signed,unsigned）;

      functionminimum（constanta,b:

ininteger）returninteger;

   endee530;

Packagebodyformat:

  packagebodypackage_nameis

      ...exportedsubprogrambodies

      ...otherinternally-useddeclarations

  endpackage_name;

Example:

  packagebodyee530is

     functionminimum（constanta,b:

integer）returnintegeris

        variablec:

integer;--localvariable

            begin

               ifa

                   c:

=a; --aismin

               else

                   c:

=b; --bismin

               endif;

               returnc; --returnminvalue

            end;

   endee530;

PackageVisibility

Tomakeallitemsofapackage"visible"toadesignunit,precedethedesireddesignunitwitha"use"statement:

Example:

  uselibrary_name.package_name.all

A"use"statementmayprecedethedeclarationofanyentityorarchitecturewhichistoutilizeitemsfromthepackage.Ifthe"use"statementprecedestheentitydeclaration,thepackageisalsovisibletothearchitecture.

User-DevelopedPackages

Compileuser-developedpackagesinyourcurrentworkinglibrary.Tomakeitvisible:

   usepackage_name.all;

Note:

'std'and'work'（yourcurrentworkinglibrary）arethetwodefaultlibraries.TheVHDL'library'statementisneededtomakethe'ieee'libraryand/oradditionallibrariesvisible.

Example

  librarylib_name;           --makelibraryvisible

  uselib_name.pkg_name.all;  --makepackagevisible

VHDLStandardPackages

STANDARD-basictypedeclarations（alwaysvisiblebydefault）

TEXTIO-ASCIIinput/outputdatatypesandsubprograms

TomakeTEXTIOvisible:

usestd.textio.all;

IEEEStandard1164Package

Thispackagecontainedinthe'ieee'librarysupportsmulti-valuedlogicsignalswithtypedeclarationsandfunctions.Tomakevisible:

  libraryieee;     --VHDLLibrarystmt

     useieee.std_logic_1164.all;

Special12-valueddatatypes/functionstointerfacewithQuickSimIIandschematicdiagrams.

  librarymgc_portable;           --SpecialMentorGraphicsLibrary

  usemgc_portable.qsim_logic.all;--Quicksimportabledatatypes

VHDLIDENTIFIERS,NUMBERS,STRINGS,ANDEXPRESSIONS

Identifiers

IdentifiersinVHDLmustbeginwithaletter,andmaycompriseanycombinationofletters,digits,andunderscores.NotethatVHDLinternallyconvertsallcharacterstoUPPERCASE.

Examples

    Memory1,Adder_Module,Bus_16_Bit

NumericConstants

Numericcontantscanbedefined,andcanbeofanybase（defaultisdecimal）.Numbersmayincludeembeddedunderscorestoimprovereadability.

Format:

base#digits#--basemustbeadecimalnumber

Examples

    16#9fba#          （hexadecimal）

    2#1111_1101_1011# （binary）

    16#f.1f#E+2       （floating-point,exponentisdecimal）

BitStringLiterals

Bitvectorconstantsarearespecifiedasliteralstrings.

Examples

    x"ffe"           （12-bithexadecimalvalue）

    o"777"           （9-bitoctalvalue）

    b"1111_1101_1101"（12-bitbinaryvalue）

ArithmeticandLogicalExpressions

ExpressionsinVHDLaresimilartothoseofmosthigh-levellanguages.Dataelementsmustbeofthetype,orsubtypesofthesamebasetype.Operatorsincludethefollowing:

∙Logical:

and,or,nand,nor,xor,not（forbooleanorbitops）

∙Relational:

=,/=,<,<=,>,>=

∙Arithmetic:

+,-,*,/,mod,rem,**,abs

（amodbtakessignofb,arembtakessignofa）

∙Concatenate:

&

（ex.a&bmakesonearray）

Examples

  a<=bnandc;

  d:

=g1*g2/3;

  Bus_16<=Bus1_8&Bus2_8;

VHDLDATATYPES

EachVHDLobjectsmustbeclassifiedasbeingofaspecificdatatype.VHDLincludesanumberofpredefineddatatypes,andallowsuserstodefinecustomdatatypesasneeded.

PredefinedScalarDataTypes（singleobjects）

VHDLStandard:

∙bitvalues:

'0','1'

∙booleanvalues:

TRUE,FALSE

∙integervalues:

-（231）to+（231-1）{SUNLimit}

∙naturalvalues:

0tointeger'high（subtypeofinteger）

∙positivevalues:

1tointeger'high（subtypeofinteger）

∙charactervalues:

ASCIIcharacters（eg.'A'）

∙timevaluesincludeunits（eg.10ns,20us）

IEEEStandard1164（packageieee.std_logic_1164.all）

∙std_ulogicvalues:

'U','X','1','0','Z','W','H','L','-'

'U'=uninitialized

'X'=unknown

'W'=weak'X'

'Z'=floating

'H'/'L'=weak'1'/'0'

'-'=don'tcare

∙std_logicresolved"std_ulogic"values

∙X01subtype{'X','0','1'}ofstd_ulogic

∙X01Zsubtype{'X','0','1','Z'}ofstd_ulogic

∙UX01subtype{'U','X','0','1'}ofstd_ulogic

∙UX01Zsubtype{'U','X','0','1','Z'}ofstd_ulogic

PredefinedVHDLAggregateDataTypes

∙bit_vectorarray（naturalrange<>）ofbit

∙stringarray（naturalrange<>）ofchar

∙textfileof"string"

IEEEStandard1164AggregateDataTypes

（Frompackage:

ieee.std_logic_1164.all）

∙std_ulogic_vectorarray（naturalrange<>）ofstd_ulogic

∙std_logic_vectorarray（naturalrange<>）ofstd_logic

Examples

   signaldbus:

bit_vector（15downto0）;

   dbus（7downto4）<="0000";（4-bitsliceofdbus）

   signalcnt:

 std_ulogic_vector（1to3）;

   variablemessage:

string（0to20）;

User-DefinedEnumerationTypes

Anenumerateddatatypecanbecreatedbyexplicitelylistingallpossiblevalues.

Example

  typeopcodesis（add,sub,jump,call）; --Typewith4values

  signalinstruc:

opcodes;                --Signalofthistype

    ...

  ifinstruc=addthen  --testforvalue'add'

    ...

Otheruser-definedtypes

Customdatatypescanincludearrays,constrainedandunconstrained,andrecordstructures.

∙Constrainedarray:

Upperandlowerindexesarespecified.

Example

  typewordisarray（0to15）ofbit;

∙Unconstrainedarray:

Indexesarespecifiedwhenasignalorvariableofthattypeisdeclared.

Examples

  typememoryisarray（integerrange<>）ofbit_vector（0to7）;

 --atypewhichisanarbitrary-sizedarrayof8-bitvectors

  variablememory256:

memory（0to255）;--a256-bytememoryarray