eda实验报告.docx
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eda实验报告
实验一LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYADDERIS
PORT（A,B:
INSTD_LOGIC_VECTOR（15downto0）;
SUM:
OUTSTD_LOGIC_VECTOR（15downto0））;
ENDADDER;
ARCHITECTUREbehavOFADDERIS
BEGIN
SUM<=（A+B）;
ENDbehav;
实验二
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYMUX4IS
PORT（A,B:
INSTD_LOGIC_VECTOR（3downto0）;
SEL:
INTEGERRANGE0TO1;
Y:
OUTSTD_LOGIC_VECTOR（3downto0））;
ENDMUX4;
ARCHITECTUREbehavOFMUX4IS
BEGIN
WITHSELSELECT
Y<=AWHEN0,
BWHEN1;
ENDbehav;
实验三
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYSEVENIS
PORT（INPUT:
INstd_logic_vector（2DOWNTO0）;
A,B,C,D,E,F,G:
OUTstd_logic）;
ENDSEVEN;
ARCHITECTUREbehavOFSEVENIS
BEGIN
PROCESS（INPUT）
BEGIN
CASEINPUTIS
WHEN"000"=>A<='1';B<='1';C<='1';D<='1';E<='1';F<='1';G<='0';
WHEN"001"=>A<='0';B<='1';C<='1';D<='0';E<='0';F<='0';G<='0';
WHEN"010"=>A<='1';B<='1';C<='0';D<='1';E<='1';F<='0';G<='1';
WHEN"011"=>A<='1';B<='1';C<='1';D<='1';E<='1';F<='0';G<='1';
WHENOTHERS=>A<='1';B<='0';C<='0';D<='1';E<='1';F<='1';G<='1';
ENDCASE;
ENDPROCESS;
ENDbehav;
八到十六位移位器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYSHIFTERIS
PORT（input:
INSTD_LOGIC_VECTOR（7DOWNTO0）;
cnt:
INSTD_LOGIC_VECTOR（1DOWNTO0）;
result:
OUTSTD_LOGIC_VECTOR（15DOWNTO0））;
ENDSHIFTER;
ARCHITECTUREBEHAVOFSHIFTERIS
BEGIN
PROCESS（input,cnt）
BEGIN
IFcnt="00"THEN
FORiIN0TO15LOOP
IFi>7THEN
result（i）<='0';
ELSE
result（i）<=input（i）;
ENDIF;
ENDLOOP;
ELSIFcnt="01"THEN
FORiIN0TO15LOOP
IFi<4THEN
result（i）<='0';
ELSIFi>11THEN
result（i）<='0';
ELSE
result（i）<=input（i-4）;
ENDIF;
ENDLOOP;
ELSIFcnt="10"THEN
FORiIN0TO15LOOP
IFi>8THEN
result（i）<=input（i-8）;
ELSEresult（i）<='0';
ENDIF;
ENDLOOP;
ELSIFcnt="11"THEN
FORiIN0TO15LOOP
IFi>=8andi<=15THEN
result（i）<='0';
ELSE
result（i）<=input（i）;
ENDIF;
ENDLOOP;
ENDIF;
ENDPROCESS;
ENDBEHAV;
十六位同步寄存器
LIBRARYIEEE;
USEIEEE.std_logic_1164.all;
USEIEEE.std_logic_unsigned.all;
ENTITYregIS
PORT（clk,clken,clr:
INstd_logic;
in_reg:
INstd_logic_vector（15downto0）;
out_reg:
OUTstd_logic_vector（15downto0））;
ENDreg;
ARCHITECTURElogicOFregIS
BEGIN
PROCESS（clk）
BEGIN
IFrising_edge（clk）THEN
IFclken='0'THEN
IFclr='1'THENout_reg<=in_reg;
ELSIFclr='0'THENout_reg<=（OTHERS=>'0'）;
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
ENDlogic;
二位异步计数器
LIBRARYIEEE;
USEIEEE.std_logic_1164.all;
USEIEEE.std_logic_unsigned.all;
ENTITYcounterIS
PORT（clk,clr:
INstd_logic;
sum:
OUTstd_logic_vector（1downto0））;
ENDcounter;
ARCHITECTURElogicOFcounterIS
BEGIN
PROCESS（clk,clr）
VARIABLEcount:
std_logic_vector（1downto0）;
BEGIN
IFclr='0'THEN
count:
="00";
sum<=count;
ELSIFrising_edge（clk）THEN
count:
=count+1;
sum<=count;
ENDIF;
ENDPROCESS;
ENDlogic;
LIBRARYIEEE;
USEIEEE.std_logic_1164.all;
USEIEEE.std_logic_unsigned.all;
ENTITYcontrolIS
PORT（clk,rst,start:
INstd_logic;
count:
INstd_logic_vector（1downto0）;
in_sel,shift:
OUTstd_logic_vector（1downto0）;
state_out:
OUTstd_logic_vector（2downto0）;
done,clken,regclr:
OUTstd_logic）;
ENDcontrol;
ARCHITECTURElogicOFcontrolIS
TYPEstate_typeIS（idle,lsb,mid,msb,err）;
SIGNALcode:
state_type;
BEGIN
PROCESS（rst,clk）
BEGIN
IFrst='1'THEN
code<=idle;
ELSIFrising_edge（clk）THEN
CASEcodeIS
WHENidle=>
IFstart='1'THEN
code<=lsb;
ELSE
code<=idle;
ENDIF;
WHENlsb=>
IFstart='0'andcount="00"THEN
code<=mid;
ELSE
code<=err;
ENDIF;
WHENmid=>
IFstart='0'andcount="10"THEN
code<=msb;
ELSIFstart='0'andcount="01"THEN
code<=mid;
ELSE
code<=err;
ENDIF;
WHENmsb=>
IFstart='0'andcount="11"THEN
code<=idle;
ELSE
code<=err;
ENDIF;
WHENerr=>
IFstart='1'THEN
code<=lsb;
ELSE
code<=err;
ENDIF;
WHENOTHERS=>
code<=idle;
ENDCASE;
endif;
ENDPROCESS;
mealy:
PROCESS（code,start,count）
BEGIN
CASEcodeIS
WHENidle=>
IFstart='1'THEN
in_sel<="XX";shift<="XX";done<='0';clken<='1';regclr<='0';
ELSE
in_sel<="XX";shift<="XX";one<='0';clken<='1';regclr<='1';
ENDIF;
WHENlsb=>
IFstart='0'andcount="00"THEN
in_sel<="00";shift<="00";done<='0';clken<='0';regclr<='1';
ELSE
in_sel<="XX";shift<="XX";done<='0';clken<='1';regclr<='1';
ENDIF;
WHENmid=>
IFstart='0'andcount="10"THEN
in_sel<="10";shift<="01";done<='0';clken<='0';regclr<='1';
ELSIFstart='0'andcount="01"THEN
in_sel<="01";shift<="01";done<='0';clken<='0';regclr<='1';
ELSE
in_sel<="XX";shift<="XX";done<='0';clken<='1';regclr<='1';
ENDIF;
WHENmsb=>
in_sel<="11";shift<="10";done<='1';clken<='0';regclr<='1';
ELSE
in_sel<="XX";shift<="XX";done<='0';clken<='1';regclr<='1';
ENDIF;
WHENerr=>
IFstart='1'THEN
in_sel<="XX";shift<="XX";done<='0';clken<='1';regclr<='0';
ELSE
in_sel<="XX";shift<="XX";done<='0';clken<='1';regclr<='1';
ENDIF;
WHENOTHERS=>
IFstart='1'THEN
in_sel<="XX";shift<="XX";done<='0';clken<='1';regclr<='0';
ELSE
in_sel<="XX";shift<="XX";done<='0';clken<='1';regclr<='1';
ENDIF;ENDCASE;
ENDPROCESSmealy;
moore:
PROCESS（code）
BEGIN
CASEcodeIS
WHENidle=>state_out<="000";
WHENlsb=>state_out<="001";
WHENmid=>state_out<="010";
WHENmsb=>state_out<="011";
WHENerr=>state_out<="100";
WHENOTHERSstate_out<="000";
ENDCASE;
ENDPROCESSmoore;
ENDlogic;
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