FPGA数字锁相环程序.docx

FPGA数字锁相环程序.docx

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FPGA数字锁相环程序

libraryieee;

useieee.std_logic_1164.all;

entityyxoris

port（x1,x2:

instd_logic;

y:

outstd_logic）;

endentityyxor;

architectureart1ofyxoris

begin

y<=x1xorx2;

endarchitectureart1;

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entityid_controlleris

port（inc,dec,clk:

instd_logic;

out1:

outstd_logic）;

endentityid_controller;

architectureart4ofid_controlleris

signaltmp:

std_logic_vector（1downto0）;signalcont:

std_logic_vector（1downto0）;signaltmp1:

std_logic;

begin

process（clk,inc,dec）

begin

if（clk'eventandclk='1'）then

ifinc='1'then

cont<="01";

elsifdec='1'then

cont<="11";

else

cont<="10";

endif;

endif;

endprocess;

process（clk,cont）

begin

ifclk'eventandclk='1'then

iftmp

tmp<=tmp+1;

else

tmp<="00";

tmp1<=nottmp1;

endif;

endif;

endprocess;

out1<=tmp1;

endarchitectureart4;

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entitydivis

port（clk:

instd_logic;

n:

instd_logic_vector（7downto0）;y:

outstd_logic）;

endentitydiv;

architectureart3ofdivis

signalk:

std_logic_vector（7downto0）;signaltmp:

std_logic;

begin

process（clk,n）is

begin

ifclk'eventandclk='1'then

ifk

k<=k+'1';

else

k<="00000000";

tmp<=nottmp;

endif;

endif;

endprocess;

y<=tmp;

endarchitectureart3;

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entitycount_kis

port（clk,updn,en,d,c,b,a:

instd_logic;

inc,dec:

outstd_logic）;

endentitycount_k;

architectureart2ofcount_kis

signalcq,k,mo:

std_logic_vector（16downto0）;signaltemp1,temp2:

std_logic;

signalinstruction:

std_logic_vector（3downto0）;begin

instruction<=d&c&b&a;

withinstructionselect

mo<="11"when"0001",

"11"when"0010",

"11"when"0011",

"11"when"0100",

"11"when"0101",

"11"when"0110",

"11"when"0111",

"11"when"1000",

"11"when"1001",

"11"when"1010",

"11"when"1011",

"11"when"1100",

"11"when"1101",

"11"when"1110",

"11"when"1111",

"11"whenothers;

process（clk,en,updn,k,cq）

begin

ifclk'eventandclk='1'then

k<=mo;

ifen='1'then

ifupdn='0'then

ifcq

cq<=cq+1;

elsecq<=（others=>'0'）;

endif;

else

ifcq>0then

cq<=cq-1;

elsecq<=k;

endif;

endif;

elsecq<=（others=>'0'）;

endif;

endif;

endprocess;

process（en,updn,cq,k）is

begin

ifen='1'then

ifupdn='0'then

ifcq=kthentemp1<='1';

elsetemp1<='0';

endif;

temp2<='0';

else

ifcq="00"thentemp2<='1';elsetemp2<='0';

endif;

temp1<='0';

endif;

elsetemp1<='0';temp2<='0';

endif;

endprocess;

inc<=temp1;dec<=temp2;

endarchitectureart2;

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entitysystemis

port（clk1,clk2,fin,en,d,c,b,a:

instd_logic;

n:

instd_logic_vector（7downto0）;

fout:

inoutstd_logic）;

endentitysystem;

architectureart5ofsystemis

componentyxoris

port（x1,x2:

instd_logic;

y:

outstd_logic）;

endcomponentyxor;

componentid_controlleris

port（inc,dec,clk:

instd_logic;

out1:

outstd_logic）;

endcomponentid_controller;

componentcount_kis

port（clk,updn,en,d,c,b,a:

instd_logic;

inc,dec:

outstd_logic）;

endcomponentcount_k;

componentdivis

port（clk:

instd_logic;

n:

instd_logic_vector（7downto0）;

y:

outstd_logic）;

endcomponentdiv;

signals1,s2,s3,s4,s5:

std_logic;

begin

u1:

yxorportmap（fin,fout,s2）;

u2:

count_kportmap（clk1,s2,en,d,c,b,a,s3,s4）;u3:

id_controllerportmap（s3,s4,clk2,s1）;

u4:

divportmap（s1,n,fout）;

endarchitectureart5;