89c51单片机论文英语文献.docx

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89c51单片机论文英语文献.docx

89c51单片机论文英语文献

AT89C51

Description

TheAT89C51isalow-power,high-performanceCMOS8-bitmicrocomputerwith4KbytesofFlashProgrammableandErasableReadOnlyMemory(PEROM)and128bytesRAM.ThedeviceismanufacturedusingAtmel’shighdensitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandardMCS-51™instructionsetandpinout.Thechipcombinesaversatile8-bitCPUwithFlashonamonolithicchip,theAtmelAT89C51isapowerfulmicrocomputerwhichprovidesahighlyflexibleandcosteffectivesolutiontomanyembeddedcontrolapplications.

Features:

•CompatiblewithMCS-51™Products

•4KBytesofIn-SystemReprogrammableFlashMemory

•Endurance:

1,000Write/EraseCycles

•FullyStaticOperation:

0Hzto24MHz

•Three-LevelProgramMemoryLock

•128x8-BitInternalRAM

•32ProgrammableI/OLines

•Two16-BitTimer/Counters

•SixInterruptSources

•ProgrammableSerialChannel

•LowPowerIdleandPowerDownModes

TheAT89C51providesthefollowingstandardfeatures:

4KbytesofFlash,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsystemtocontinuefunctioning.ThePowerDownModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset.

BlockDiagram

PinDescription:

VCCSupplyvoltage.

GNDGround.

Port0

Port0isan8-bitopendrainbidirectionalI/Oport.AsanoutputporteachpincansinkeightTTLinputs.Whenisarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.

Port0mayalsobeconfiguredtobethemultiplexedloworderaddress/databusduringaccessestoexternalprogramanddatamemory.InthismodeP0hasinternalpullups.

Port0alsoreceivesthecodebytesduringFlashprogramming,andoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.

Port1

Port1isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.

Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.

Port2

Port2isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.

Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplicationitusesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.

Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.

Port3

Port3isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepullups.

Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelow:

Portpin

alternatefunctions

P3.0

rxd(serialinputport)

P3.1

txd(serialoutputport)

P3.2

^int0(externalinterrupt0)

P3.3

^int1(externalinterrupt1)

P3.4

t0(timer0externalinput)

P3.5

t1(timer1externalinput)

P3.6

^WR(externaldatamemorywritestrobe)

P3.7

^rd(externaldatamemoryreadstrobe)

Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.

RST

Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.

ALE/PROG

AddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(PROG)duringFlashprogramming.

InnormaloperationALEisemittedataconstantrateof1/6theoscillatorfrequency,andmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduringeachaccesstoexternalDataMemory.

Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.

PSEN

ProgramStoreEnableisthereadstrobetoexternalprogrammemory.

WhentheAT89C51isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.

EA/VPP

ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.

EAshouldbestrappedtoVCCforinternalprogramexecutions.

Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming,forpartsthatrequire12-voltVPP.

XTAL1

Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.

XTAL2

Outputfromtheinvertingoscillatoramplifier.

OscillatorCharacteristics

XTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillator,asshowninFigure1.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdrivenasshowninFigure2.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.

IdleMode

Inidlemode,theCPUputsitselftosleepwhilealltheonchipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.

Itshouldbenotedthatwhenidleisterminatedbyahardwarereset,thedevicenormallyresumesprogramexecution,fromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.ToeliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleisterminatedbyreset,theinstructionfollowingtheonethatinvokesIdleshouldnotbeonethatwritestoaportpinortoexternalmemory.

StatusofExternalPinsDuringIdleandPowerDownModes

mode

Programmemory

ALE

^psen

Port0

Port1

Port2

Port3

idle

internal

1

1

data

data

data

Data

Idle

External

1

1

float

Data

data

Data

Powerdown

Internal

0

0

Data

Data

Data

Data

Powerdown

External

0

0

float

data

Data

data

PowerDownMode

Inthepowerdownmodetheoscillatorisstopped,andtheinstructionthatinvokespowerdownisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthepowerdownmodeisterminated.Theonlyexitfrompowerdownisahardwarereset.ResetredefinestheSFRsbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.

ProgramMemoryLockBits

Onthechiparethreelockbitswhichcanbeleftunprogrammed(U)orcanbeprogrammed(P)toobtaintheadditionalfeatureslistedinthetablebelow:

LockBitProtectionModes

Programlockbits

Protectiontype

Lb1

Lb2

Lb3

1

U

U

U

Noprogramlockfeatures

2

 

P

 

U

 

U

 

Movcinstructionsexecutedfromexternalprogrammemoryaredisablefromfetchingcodebytesfrominternalmemory,^eaissampledandlatchedonreset,andfurtherprogrammingoftheflashdisabled

3

P

P

U

Sameasmode2,alsoverifyisdisable.

4

P

P

P

Sameasmode3,alsoexternalexecutionisdisabled.

Whenlockbit1isprogrammed,thelogiclevelattheEApinissampledandlatchedduringreset.Ifthedeviceispoweredupwithoutareset,thelatchinitializestoarandomvalue,andholdsthatvalueuntilresetisactivated.ItisnecessarythatthelatchedvalueofEAbeinagreementwiththecurrentlogiclevelatthatpininorderforthedevicetofunctionproperly.

ProgrammingtheFlash:

TheAT89C51isnormallyshippedwiththeon-chipFlashmemoryarrayintheerasedstate(thatis,contents=FFH)andreadytobeprogrammed.Theprogramminginterfaceacceptseitherahigh-voltage(12-volt)oralow-voltage(VCC)programenablesignal.ThelowvoltageprogrammingmodeprovidesaconvenientwaytoprogramtheAT89C51insidetheuser’ssystem,whilethehigh-voltageprogrammingmodeisco

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