Application NoteQAN20 Digital UART Design in HDL.docx

Application NoteQAN20 Digital UART Design in HDL.docx

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ApplicationNoteQAN20DigitalUARTDesigninHDL

ApplicationNote:

QAN20DigitalUARTDesigninHDL

Introduction

Theuseofhardwaredescriptionlanguage（HDL）isbecomingamoredominantfactor,whendesigningandverifyingFPGAdesigns.Theuseofbehaviorleveldescriptionnotonlyincreasesthedesignproductivity,butalsoprovidesuniqueadvantagesinthedesignverification.ThemostdominantHDLstodayarecalledVerilogandVHDL.ThisapplicationnotewillillustratetheuseofVerilogindesignandverificationofadigitalUART（UniversalAsynchronousReceiver&Transmitter）.

DefiningtheUART.

TheUARTconsistsoftwoindependentHDLmodules.Onemoduleimplementsthe

transmitter,whiletheothermoduleimplementsthereceiver.Thetransmitterandreceivermodulescanbecombinedatthetoplevelofthedesign,foranycombinationsoftransmitterandreceiverchannelsrequired.Datacanbewrittentothetransmitterandreadoutfromthereceiver,allthroughasingle8bitbi-directionalCPUinterface.Addressmappingforthetransmitterandreceiverchannelscaneasilybebuildinto

theinterfaceatthetoplevelofthedesign.Bothmodulesshareacommonmasterclockcalledmclkx16.Withineachmodulemclkx16aredivideddowntoindependentbaudrateclocks.

UARTfunctionaloverview.

AbasicoverviewoftheUARTisshownbelow.Atthelefthandsideisshown“transmitholdregister”,“transmitshiftregister”andthetransmitter“controllogic”block,allcontainedwithinthetransmittermodulecalled“txmit”.Attherighthandsideisshownthe“receiveshiftregister”,“receiveholdregister”andthereceiver“controllogic”block,allcontainedwithinthereceivermodulecalled“rxcver”.Thetwomoduleshaveseparateinputsandoutputsformostoftheircontrollines,onlythebi-directionaldatabus,masterclockandresetlinesaresharedbybothmodules.

TheUARTstandarddataformat.

Infigure3isshowntheUARTserialdataformat.Serialdataarecontainedwithinframesof8databits,aswellascodedinformationbits.Betweensuccessivetransmissions,thetransmissionlineisheldhigh.Atransmissionisinitializedbyaleadinglowstartbit.Nexttotheleadinglowstartbitcomes8bitsofdatainformation,beginningwiththeLSBandafterwardsrepresentedatincreasingsignificanceorderuptotheMSB.Nexttothe8databitscomestheparitybit,representingtheparityresultofthe8databits.Theparitybitcanbeencodedtruebasedonevenparityoroddparitymode.Nexttotheparitybitcomesatrailinghighstopbitindicatingtheendofadataframe..

UARTtimingdiagrams.

Belowisshown,howdatawrittentothe“transmitholdregister”getsloadedintothe“transmitshiftregister”,andattherisingedgeofthebaudrateclock,shiftedtotxoutput.

Belowisshown,howdatagetsshiftedfromrxinputtothe“receiveshiftregister”,andafterwardsloadedintothe“receiveholdregister”.Finallythereceiverraises“rxrdy”flag.

TheTransmittermodule.

Themasterclockcalledmclkx16aredivideddowntotheproperbaudratecalledtxclkandequalstomclkx16/16.Datawritteninparallelformattothemodulearelatchedinternally,andshiftedinserialformattothetxoutputatthefrequencyofthebaudrateclock.DatashiftedtothetxoutputfollowstheUARTdataformatshowninfig.3.

Behavioraldescriptionofthetransmitter.

Thetransmitterwaitsfornewdatatobewrittentothemodule.Whennewdataarewrittenatransmitsequenceisinitialized.Datathatwaswritteninparalleltothemodulegetstransmittedasserialdataframesatthetxoutput.Whennotransmitsequenceareinplace,thetxoutputisheldhigh.

Implementationofthetransmittermodule.

CreatinglogicinVerilogstartswiththemoduleportdeclaration.Heredefinessignals,thatareportedtoandfromthemodule.Nodirectionarespecifiedatthispoint.

Nexttoportdefinitionscomesportdirections.Directionsarespecifiedasinput,outputorinout（bidirectional）,andcanbereferredtointable1.Nexttothespecificationofportdirectionscomesdeclarationofinternalsignals.InternalsignalsinVerilogaredeclaredas“wire”or“reg”datatypes.Signalsofthe“wire”typeareusedforcontinuosassignments,alsocalledcombinatorialstatements.Signalsofthe“reg”typeareusedforassignmentswithintheVerilog“always”block,oftenusefor

sequentiallogicassignments,butnotnecessarily.ForfurtherexplanationseeaVerilogreferencebook.Datatypesoftheinternalsignalsofthemodulecanbereferredtointable3.Wehavenowpassedbyallnecessarydeclarations,andarenowreadytolookattheactualimplementation.Usinghardwaredescriptionlanguageallowsustodescribethefunctionofthetransmitterinamorebehavioralmanner,ratherthanfocusonit’sactualimplementationatgatelevelInsoftwareprogramminglanguage,functionsandproceduresbreakslargerprogramsintomorereadable,manageableandcertainlymaintainablepieces.TheVeriloglanguageprovidesfunctionsandtasksas

constructs,analogoustosoftwarefunctionsandprocedures.AVerilogfunctionandtaskareusedastheequivalenttomultiplelinesofVerilogcode,wherecertaininputsorsignalsaffectscertainoutputsorvariables.Theuseoffunctionsandtasksusuallytakesplacewheremultiplelinesofcodearerepeatedlyusedinadesign,andhencemakesthedesigneasiertoreadandcertainlymaintain.AVerilogfunction

canhavemultipleinputs,butalwayshaveonlyoneoutput,whiletheVerilogtaskcanhavebothmultipleinputs,andmultipleoutputsandeveninsomecases,nonofeach.BelowisshowntheVerilogtask,thatholdallnecessarysequentialstatements,todescribethetransmitterinthe“shift”mode.

Wehereseethetwotagbitscalledtag1andtag2concatenatedtothe“transmitshiftregister.Similartaskswerecreatedtodescribethetransmitterin“idle”and“load”

modes.ByusingtheseVerilogtasks,wecannowcreateavery“easytoread”behavioralmodeloftheholetransmitprocess.

Iftxdoneandtxdatardybotharetrue,thetransmitterenterloadmode.Nexttotheloadmode,thetransmitterentersshiftmode.Attherisingedgeofthebaudrateclock,thecontentsoftsrareshiftedtothetxoutput.Paritygenerationtakesplaceduringshiftingofthetsr,asshownbelow.

It’simportanttonote,thatthetsrarezerofilledduringtransmission.Thecombinationofthetwotrailingtagbitsandthezerofilledtsrindicatesthedifferentstatesduringshifting.Paritycycleishighoncyclenexttolastcycle,thatmeanswhentsr[1]getstag2.

Txdoneishighwhenshiftingisover,thismeanswhentxgetstag2.

Basedonthedifferentstatesduringthetransmissionsequence,“databits”,“paritybit”or“stopbit”areultiplexedtothetxoutput.

Simulationofatransmitsequence

Thecontentsofthedatabusarelatchedintothrattherisingedgeofwrite.Atthenextrisingedgeoftxclk,thecontentsofthrareloadedintotsr,theactivelowstartbitisassertedtotx,andthetxrdyflagindicates,thatthragainisreadyfornewdatatobewritten.Ateachrisingedgeoftxclk,thecontentsoftsrisshiftedtotx.Paritygenerationtakesplaceduringshiftingofdata.Paritycycleishighonecyclenexttolastcycle,andtxgetstheparityresult.Theinternaltxdoneishighwhenshiftingisover,andtheactivehighstopbitisassertedtotx.

Forfurtherdetailsontheimplementationcanbereferredtointhedesignsourcefileavailablefrom

TheReceivermodule.

Themasterclockmclkx16aredivideddowntotheproperbaudrateclockcalledrxclk,andequalstomclkx16/16.Serialdatatobereceivedattherxinputofthemodule,mustfollowtheUARTdataformatshowninfig.3.Datareceivedinserialformatcanbereadoutinparallelformat,throughthe8bitdatabus.

Behavioraldescriptionofthereceiver.

Betweensuccessivetransmissions,thetransmissionlineisheldhigh,accordingtostandardUARTbehavior.Thereceiverwaitsin“idle”modefortherxinputtogolow.Atthefallingedgeofrxthereceiverenter“hunting”mode,nowsearchingforavalidstartbitofanewdataframetobereceived.Ifavalidstartbitisdetected,thereceiverenter“shiftdata”mode.Ifaninvalidstartbitisdetected,thereceiverreturnsto“idle”mode.Duringreceiveofadataframe,variousparityanderrorchecksareperformed.Whenacompletedataframehasbeenreceivedthereceiverreturnstoidlemode.Thebasicoperationofthereceiverworksasshownbelow,

Thefrequencyofrxclkareequaltomclkx16/16,andthefirstrisingedgeoftherxclkwillalwaysoccuratthecenterpointofthestartbit.Belowisshown,howgenerationofthebaudrateclockrxclkaresynchronizedtothecenterpointsofthestartbitandthefollowingdatabits.

Implementationofthereceivermodule.

Inordertocreateaneasytoreadandeasytomaintainbehavioralmodelofthereceiver,twoVerilogtasksarewrittentodescribethedifferentmodesofthereceiver.TheVerilogtaskcalled“idle_reset”holdsallnecessarysequentialstatementstodescribethereceiveratresetcondition,andwhenthereceiverisinit’sidlemode.

Whenthereceiverisnotatit’sresetcondition,andnotinit’sidlemode,thereceiversamplesdataattherxinput,shiftsthedatatothe“receiveshiftregister”,andgeneratesparitybasedontheincomingdata.TheVerilogtaskcalled“shift_data”holdsallnecessarysequentialstatementstodescribeallaboveactions.

UsingthetwoVerilogtasksdescribedabove,wearenowabletocreatethebehavioralleveldescriptionofthereceiveratit’sresetcondition,idlemodeorwhenshiftingindata.Allaboveactionsissynchronoustothebaudrateclockcal