用VHDL语言实现拔河电路功能Word文件下载.docx
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ENDCOUNT_100;
ARCHITECTUREfwmOFCOUNT_100IS
SIGNALhi_tmp,lo_tmp:
STD_LOGIC_VECTOR(3DOWNTO0);
--SIGNALload_cnt:
STD_LOGIC_VECTOR(1DOWNTO0);
BEGIN
--load_cnt<
=load&
hi_lo;
--数据写入与置数位控制的并置
PROCESS(clk,clr)
--hi_lo='
1'
时为高位置数,hi_lo='
0'
时为低位置数
--VARIABLEq_tmp:
BEGIN
IFclr='
THENhi_tmp<
="
0000"
;
lo_tmp<
--异步清零
ELSIFclk'
EVENTANDclk='
THEN
--IFload_cnt="
10"
THEN--低位置数
--IFdate_in>
1010"
THENlo_tmp<
1001"
--ELSElo_tmp<
=date_in;
--ENDIF;
--ELSIFload_cnt="
11"
THEN--高位置数
THENhi_tmp<
--ELSEhi_tmp<
01"
ORload_cnt="
00"
THEN
IFlo_tmp="
THEN--低位等于9
IFhi_tmp/="
THEN--如果高位不等于9
lo_tmp<
hi_tmp<
=hi_tmp+1;
--那么高位加1
ELSE
hi_tmp<
--ELSElo_tmp<
--除此之外,低位9保持不变
ENDIF;
ELSElo_tmp<
=lo_tmp+1;
--如果低位不是9,那么低位加1
ENDIF;
--ENDIF;
ENDIF;
ENDPROCESS;
lo_out<
=lo_tmp;
--低位信号赋值给低位输出端
hi_out<
=hi_tmp;
--高位信号赋值给高位输出端
ENDfwm;
--以下为计算胜的局数的10进制计数器
ENTITYCOUNT_10IS
PORT(clk,clr:
COUNT_10_OUT:
ENDCOUNT_10;
ARCHITECTUREfwmOFCOUNT_10IS
SIGNALCOUNT_10_TMP:
BEGIN
BEGINIFclr='
THENCOUNT_10_TMP<
="
COUNT_10_TMP<
=COUNT_10_TMP+1;
IFCOUNT_10_TMP="
THEN--如果加到十,归零
COUNT_10_TMP<
ENDIF;
ENDPROCESS;
COUNT_10_OUT<
=COUNT_10_TMP;
--以下为分频器实体电路
ENTITYFPIS
PORT(clk_in:
INSTD_LOGIC;
clk_out:
OUTSTD_LOGIC);
ENDFP;
ARCHITECTUREfwmOFFPIS
CONSTANTM:
INTEGER:
=25000000;
--50M分频到1HZ
SIGNALFP_TMP:
STD_LOGIC;
PROCESS(clk_in)
VARIABLECOUNT:
=0;
BEGIN
IFclk_in'
EVENTANDclk_in='
COUNT:
=COUNT+1;
--计数器+1
IFCOUNT<
=MTHENFP_TMP<
='
ELSIFCOUNT<
M*5THENFP_TMP<
ELSECOUNT:
ENDIF;
ENDIF;
clk_out<
=FP_TMP;
--以下为七段数码管显示译码电路设计实体
ENTITYDISIS
PORT(date_in:
INSTD_LOGIC_VECTOR(3DOWNTO0);
dis_out:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDDIS;
ARCHITECTUREfwmOFDISIS
PROCESS(date_in)
CASEdate_inIS
WHEN"
=>
dis_out<
1000000"
--显示0;
0001"
1111001"
--显示1;
0010"
0100100"
--显示2;
0011"
0110000"
--显示3;
0100"
0011001"
--显示4;
0101"
0010010"
--显示5;
0110"
0000010"
--显示6;
0111"
1111000"
--显示7;
1000"
0000000"
--显示8;
0010000"
--显示9;
WHENOTHERS=>
dis_out<
1111111"
--不显示;
ENDCASE;
--以下为8位无符号整数比较器设计实体
ENTITYCOMPAREIS
PORT(a,b:
INSTD_LOGIC_VECTOR(7DOWNTO0);
eq,lt,gt:
OUTSTD_LOGIC);
ENDCOMPARE;
ARCHITECTUREfwmOFCOMPAREIS
PROCESS(a,b)
BEGIN
eq<
lt<
gt<
IFa=bTHENeq<
IFa<
bTHENlt<
IFa>
bTHENgt<
--以下为采用结构化描述test_6--
ARCHITECTUREfwmOFtest4IS
COMPONENTCOUNT_100
PORT(clk,clr:
--date_in:
ENDCOMPONENTCOUNT_100;
COMPONENTDIS
PORT(date_in:
dis_out:
ENDCOMPONENTDIS;
COMPONENTCOMPARE
PORT(a,b:
eq,lt,gt:
ENDCOMPONENTCOMPARE;
COMPONENTCOUNT_10
ENDCOMPONENTCOUNT_10;
COMPONENTFP
ENDCOMPONENTFP;
SIGNALtem_lo_1,tem_hi_1,tem_lo_2,tem_hi_2:
--定义百进制计数器输出中间变量
SIGNALCLK_OUT:
--定义分频器输出中间信号
SIGNALCOUNT_10_DATE_OUT1,COUNT_10_DATE_OUT2:
STD_LOGIC_VECTOR(3DOWNTO0);
--定义十进制计数器输出中间变量
SIGNALlt_mid,eq_mid,gt_mid:
STD_LOGIC;
--定义比较器输出中间变量
---元件例化语句---
U0:
FPPORTMAP(clk_in=>
CLOCK_IN,clk_out=>
CLK_OUT);
U1:
COUNT_100PORTMAP(clk=>
KEY1,CLR=>
CLK_OUT,
lo_out=>
tem_lo_1,
hi_out=>
tem_hi_1);
U2:
KEY2,CLR=>
tem_lo_2,
tem_hi_2);
U3:
DISPORTMAP(date_in=>
dis_out=>
HEX0);
U4:
tem_hi_1,
HEX1);
U5:
HEX2);
U6:
tem_hi_2,
HEX3);
U7:
COMPAREPORTMAP(a(0)=>
tem_lo_1(0),a
(1)=>
tem_lo_1
(1),a
(2)=>
tem_lo_1
(2),a(3)=>
tem_lo_1(3),
a(4)=>
tem_hi_1(0),a(5)=>
tem_hi_1
(1),a(6)=>
tem_hi_1
(2),a(7)=>
tem_hi_1(3),
b(0)=>
tem_lo_2(0),b
(1)=>
tem_lo_2
(1),b
(2)=>
tem_lo_2
(2),b(3)=>
tem_lo_2(3),
b(4)=>
tem_hi_2(0),b(5)=>
tem_hi_2
(1),b(6)=>
tem_hi_2
(2),b(7)=>
tem_hi_2(3),
lt=>
lt_mid,eq=>
eq_mid,gt=>
gt_mid);
U8:
COM(0),eq=>
COM
(1),gt=>
COM
(2));
U9:
COUNT_10PORTMAP(clk=>
lt_mid,clr=>
KEY3,
COUNT_10_OUT=>
COUNT_10_DATE_OUT1);
U10:
gt_mid,clr=>
COUNT_10_DATE_OUT2);
U11:
COUNT_10_DATE_OUT1,
HEX4);
U12:
COUNT_10_DATE_OUT2,
HEX5);
五、实验结果
1、没加五秒的脉冲之前的结果:
2、加了五秒脉冲后的结果