EX1基于QUARTUS MODELSIM波形器仿真Word下载.docx
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vlibcycloneii
vmapcycloneiicycloneii
vcom-workcycloneiic:
/altera/80/quartus/eda/sim_lib/cycloneii_atoms.vhd
/altera/80/quartus/eda/sim_lib/cycloneii_components.vhd
/altera/80/quartus/eda/sim_lib/altera_mf_components.vhd
/altera/80/quartus/eda/sim_lib/altera_mf.vhd
vcom-workcycloneiid:
注：
第一次在新建计算机上运行QUARTUS与MODELSIM时进行
220model.vhd是work.lpm_components
路径要根据实际安装目录来定，有的计算机可能是d:
/altera/80/quartus/eda/sim_lib/……
设计步骤
1建立工程
2在project窗口导入wave.vho
3编译wave.vho文件
其由QUARTUS生成
4建立测试台文件
以WAVE.VHO为源生成并编辑WAVE_TB.VHD文件，仿真WAVE_TB文件
图1建立工程
altera库仿真库放在modelsim安装目录下的\cycloneii下，要映射cycloneii库到modelsim安装目录下的\cycloneii。
图2建立altera仿真库
图3开始仿真
选中SDF选项，导入延时文件*.sdo（后仿真）
在transcript窗键入
Vsim>
addwave*
run140us
选择dout信号，选择format->
analog，REDIX->
UNSIGNED
可以用analog（custom）改变数据范围等
图4前仿真结果
附录1
源文件：
见附录2
测试台文件如下：
LIBRARYcycloneii
LIBRARYieee;
USEIEEE.STD_LOGIC_SIGNED.ALL;
USEcycloneii.cycloneii_components.all;
USEieee.std_logic_1164.all;
ENTITYwave_tbIS
END;
--cyclone为MODELSIM中ALTERA库的名称
ARCHITECTUREwave_tb_archOFwave_tbIS
SIGNALdout:
std_logic_vector（7downto0）;
SIGNALdac_wr:
std_logic;
SIGNALdac_cs:
SIGNALswitch:
std_logic_vector（2downto0）:
="
000"
;
SIGNALdac_ab:
SIGNALclk:
std_logic:
='
0'
COMPONENTwave
PORT（
dout:
outstd_logic_vector（7downto0）;
dac_wr:
outstd_logic;
dac_cs:
switch:
instd_logic_vector（2downto0）;
dac_ab:
clk:
instd_logic）;
ENDCOMPONENT;
BEGIN
DUT:
wave
PORTMAP（
dout=>
dout,
dac_wr=>
dac_wr,
dac_cs=>
dac_cs,
switch=>
switch,
dac_ab=>
dac_ab,
clk=>
clk）;
process（clk）
begin
clk<
=notclkafter10ns;
endprocess;
附录2
设计源文件
LIBRARYIEEE,cycloneii;
USEIEEE.std_logic_1164.all;
USEcycloneii.cycloneii_components.all;
ENTITYwaveIS
PORT（
OUTstd_logic;
INstd_logic;
OUTstd_logic_vector（7DOWNTO0）;
INstd_logic_vector（2DOWNTO0）
）;
ENDwave;
ARCHITECTUREstructureOFwaveIS
SIGNALgnd:
std_logic:
='
;
SIGNALvcc:
1'
SIGNALdevoe:
SIGNALdevclrn:
SIGNALdevpor:
SIGNALww_devoe:
std_logic;
SIGNALww_devclrn:
SIGNALww_devpor:
SIGNALww_dac_wr:
SIGNALww_clk:
SIGNALww_dac_cs:
SIGNALww_dac_ab:
SIGNALww_dout:
std_logic_vector（7DOWNTO0）;
SIGNALww_switch:
std_logic_vector（2DOWNTO0）;
SIGNAL\inst|altsyncram_component|auto_generated|ram_block1a0_PORTAADDR_bus\:
std_logic_vector（5DOWNTO0）;
SIGNAL\inst|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus\:
SIGNAL\clk~clkctrl_INCLK_bus\:
std_logic_vector（3DOWNTO0）;
SIGNAL\inst2|clk1~clkctrl_INCLK_bus\:
SIGNAL\inst4|Add1~114_combout\:
SIGNAL\inst4|Add1~117\:
SIGNAL\inst4|Add1~118_combout\:
SIGNAL\inst4|Add0~357_combout\:
SIGNAL\inst4|Add0~363_combout\:
SIGNAL\inst6|Add0~60_combout\:
SIGNAL\inst6|Add0~61\:
SIGNAL\inst6|Add0~62_combout\:
SIGNAL\inst6|Add0~63\:
SIGNAL\inst6|Add0~64_combout\:
SIGNAL\inst6|Add0~65\:
SIGNAL\inst6|Add0~66_combout\:
SIGNAL\inst6|Add0~67\:
SIGNAL\inst6|Add0~68_combout\:
SIGNAL\inst2|Add0~67\:
SIGNAL\inst2|Add0~68_combout\:
SIGNAL\inst7|Mux0~158_combout\:
SIGNAL\inst7|Mux1~54_combout\:
SIGNAL\inst7|Mux2~54_combout\:
SIGNAL\inst6|clk1~regout\:
SIGNAL\inst4|Add0~374_combout\:
SIGNAL\inst6|Equal0~41_combout\:
SIGNAL\inst6|clk1~27_combout\:
SIGNAL\inst6|coun~83_combout\:
SIGNAL\inst6|coun~84_combout\:
SIGNAL\inst2|coun~83_combout\:
SIGNAL\clk~clkctrl_outclk\:
SIGNAL\clk~combout\:
SIGNAL\inst3|q~2_combout\:
SIGNAL\inst3|q~regout\:
SIGNAL\inst7|Mux0~156_combout\:
SIGNAL\inst5|num[3]~312_combout\:
SIGNAL\inst5|num[0]~_wirecell_combout\:
SIGNAL\inst5|num[3]~313\:
SIGNAL\inst5|num[4]~314_combout\:
SIGNAL\inst5|num[4]~315\:
SIGNAL\inst5|num[5]~316_combout\:
SIGNAL\inst5|num[5]~317\:
SIGNAL\inst5|num[6]~318_combout\:
SIGNAL\inst5|num[7]~322_combout\:
SIGNAL\inst5|Equal0~52_combout\:
SIGNAL\inst5|num[7]~323_combout\:
SIGNAL\inst5|num~324_combout\:
SIGNAL\inst5|num[6]~319\:
SIGNAL\inst5|num[7]~320_combout\:
SIGNAL\inst4|LessThan0~102_combout\:
SIGNAL\inst4|LessThan0~103_combout\:
SIGNAL\inst4|Add0~377_combout\:
SIGNAL\inst4|Add0~358\:
SIGNAL\inst4|Add0~359_combout\:
SIGNAL\inst4|Add0~376_combout\:
SIGNAL\inst4|Add0~360\:
SIGNAL\inst4|Add0~361_combout\:
SIGNAL\inst4|Add0~375_combout\:
SIGNAL\inst4|Add0~362\:
SIGNAL\inst4|Add0~364\:
SIGNAL\inst4|Add0~365_combout\:
SIGNAL\inst4|Add0~373_combout\:
SIGNAL\inst4|Add0~366\:
SIGNAL\inst4|Add0~368\:
SIGNAL\inst4|Add0~369_combout\:
SIGNAL\inst4|Add0~371_combout\:
SIGNAL\inst7|Mux0~159_combout\:
SIGNAL\inst7|Mux0~160_combout\:
SIGNAL\inst7|Mux0~157_combout\:
SIGNAL\inst4|Add0~367_combout\:
SIGNAL\inst4|Add0~372_combout\:
SIGNAL\inst4|Add1~105_cout\:
SIGNAL\inst4|Add1~107\:
SIGNAL\inst4|Add1~109\:
SIGNAL\inst4|Add1~111\:
SIGNAL\inst4|Add1~113\:
SIGNAL\inst4|Add1~115\:
SIGNAL\inst4|Add1~116_combout\:
SIGNAL\inst7|Mux1~55_combout\:
SIGNAL\inst7|Mux1~56_combout\:
SIGNAL\inst7|Mux2~55_combout\:
SIGNAL\inst7|Mux2~56_combout\:
SIGNAL\inst7|Mux3~54_combout\:
SIGNAL\inst4|Add1~112_combout\:
SIGNAL\inst7|Mux3~55_combout\:
SIGNAL\inst7|Mux3~56_combout\:
SIGNAL\inst4|Add1~110_combout\:
SIGNAL\inst2|Add0~60_combout\:
SIGNAL\inst2|coun~84_combout\:
SIGNAL\inst2|Add0~61\:
SIGNAL\inst2|Add0~63\:
SIGNAL\inst2|Add0~64_combout\:
SIGNAL\inst2|Add0~62_combout\:
SIGNAL\inst2|Add0~65\:
SIGNAL\inst2|Add0~66_combout\:
SIGNAL\inst2|Equal0~41_combout\:
SIGNAL\inst2|clk1~27_combout\:
SIGNAL\inst2|clk1~regout\:
SIGNAL\inst2|clk1~clkctrl_outclk\:
SIGNAL\inst1|lpm_counter_component|auto_generated|counter_comb_bita0~combout\:
SIGNAL\inst1|lpm_counter_component|auto_generated|counter_comb_bita0~COUT\:
SIGNAL\inst1|lpm_counter_component|auto_generated|counter_comb_bita1~combout\:
SIGNAL\inst1|lpm_counter_component|auto_generated|counter_comb_bita1~COUT\:
SIGNAL\inst1|lpm_counter_component|auto_generated|counter_comb_bita2~combout\:
SIGNAL\inst1|lpm_counter_component|auto_generated|counter_comb_bita2~COUT\:
SIGNAL\inst1|lpm_counter_component|auto_generated|counter_comb_bita3~combout\:
SIGNAL\inst1|lpm_counter_component|auto_generated|counter_comb_bita3~COUT\:
SIGNAL\inst1|lpm_counter_component|auto_generated|counter_comb_bita4~combout\:
SIGNAL\inst1|lpm_counter_component|auto_generated|counter_comb_bita4~COUT\:
SIGNAL\inst1|lpm_counter_component|auto_generated|counter_comb_bita5~combout\:
SIGNAL\inst7|Mux4~54_combout\:
SIGNAL\inst7|Mux4~55_combout\:
SIGNAL\inst7|Mux4~56_combout\:
SIGNAL\inst4|Add1~108_combout\:
SIGNAL\inst7|Mux0~161_combout\:
SIGNAL\inst7|Mux5~15_combout\:
SIGNAL\inst7|Mux5~16_combout\:
SIGNAL\inst4|Add1~106_combout\:
SIGNAL\inst7|Mux6~15_combout\:
SIGNAL\inst7|Mux6~16_combout\:
SIGNAL\inst7|Mux7~31_combout\:
SIGNAL\inst4|temp[0]~111_combout\:
SIGNAL\inst7|Mux7~32_combout\:
SIGNAL\inst5|num\:
SIGNAL\inst4|temp\:
SIGNAL\inst1|lpm_counter_component|auto_generated|safe_q\:
SIGNAL\inst2|coun\:
std_logic_vector（4DOWNTO0）;
SIGNAL
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