SPI总线Word格式.docx
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SS:
从属选择;
芯片上“从属选择”(slave-select)的引脚数决定了可连到总线上的器件数量。
在SPI传输中,数据是同步进行发送和接收的。
数据传输的时钟基于来自主处理器的时钟脉冲(好像也可以是IO上的电平的模拟时钟),摩托罗拉没有定义任何通用SPI的时钟规范。
然而,最常用的时钟设置基于时钟极性(CPOL)和时钟相位(CPHA)两个参数,CPOL定义SPI串行时钟的活动状态,而CPHA定义相对于SO-数据位的时钟相位。
CPOL和CPHA的设置决定了数据取样的时钟沿。
数据方向和通信速度
SPI传输串行数据时首先传输最高位。
波特率可以高达5Mbps,具体速度大小取决于SPI硬件。
例如,Xicor公司的SPI串行器件传输速度能达到5MHz。
SPI总线接口及时序
SPI总线包括1根串行同步时钟信号线以及2根数据线。
SPI模块为了和外设进行数据交换,根据外设工作要求,其输出串行同步时钟极性和相位可以进行配置,时钟极性(CPOL)对传输协议没有重大的影响。
如果CPOL=0,串行同步时钟的空闲状态为低电平;
如果CPOL=1,串行同步时钟的空闲状态为高电平。
时钟相位(CPHA)能够配置用于选择两种不同的传输协议之一进行数据传输。
如果CPHA=0,在串行同步时钟的第一个跳变沿(上升或下降)数据被采样;
如果CPHA=1,在串行同步时钟的第二个跳变沿(上升或下降)数据被采样。
SPI主模块和与之通信的外设音时钟相位和极性应该一致。
SPI接口时序如图3、图4所示。
SPI是一个环形总线结构,由ss(cs)、sck、sdi、sdo构成,其时序其实很简单,主要是在sck的控制下,两个双向移位寄存器进行数据交换。
假设下面的8位寄存器装的是待发送的数据10101010,上升沿发送、下降沿接收、高位先发送。
那么第一个上升沿来的时候数据将会是sdo=1;
寄存器=0101010x。
下降沿到来的时候,sdi上的电平将所存到寄存器中去,那么这时寄存器=0101010,sdi,这样在8个时钟脉冲以后,两个寄存器的内容互相交换一次。
这样就完成里一个spi时序。
例子
假设主机和从机初始化就绪:
并且主机的sbuff=0xaa(10101010),从机的sbuff=0x55(01010101),下面将分步对spi的8个时钟周期的数据情况演示一遍:
假设上升沿发送数据.
脉冲(SCLK)
主机sbuff(主端发送)
从机sbuff(主端接受)
sdi串行输入到主端
sdo串行输出从主端
10101010
01010101
1上
0101010x
1010101x
1
1下
01010100
10101011
2上
1010100x
0101011x
2下
10101001
01010110
3上
0101001x
1010110x
3下
01010010
10101101
4上
1010010x
0101101x
4下
10100101
01011010
5上
0100101x
1011010x
5下
01001010
10110101
6上
1001010x
0110101x
6下
10010101
01101010
7上
0010101x
1101010x
7下
00101010
11010101
8上
8下
这样就完成了两个寄存器8位的交换,上面的上表示上升沿、下表示下降沿,sdi、sdo相对于主机而言的。
其中ss引脚作为主机的时候,从机可以把它拉底被动选为从机,作为从机的是时候,可以作为片选脚用。
根据以上分析,一个完整的传送周期是16位,即两个字节,因为,首先主机要发送命令过去,然后从机根据主机的命令准备数据,主机在下一个8位时钟周期才把数据读回来,主机产生时钟SCLK,而数据又必须依靠边沿启动才能传送。
SPI总线是Motorola公司推出的三线同步接口,同步串行3线方式进行通信:
一条时钟线SCK,一条数据输入线MOSI,一条数据输出线MISO;
用于CPU与各种外围器件进行全双工、同步串行通讯。
SPI主要特点有:
可以同时发出和接收串行数据;
可以当作主机或从机工作;
提供频率可编程时钟;
发送结束中断标志;
写冲突保护;
总线竞争保护等。
图3示出SPI总线工作的四种方式,其中使用的最为广泛的是SPI0和SPI3方式(实线表示):
图2
SPI总线四种工作方式
Preface
Withthisarticle,thepossibilitiesofserialcommunicationwithperipheraldevicesviaSPI(SerialPeripheralInterface)willbediscussed.Moreandmoreserialbussystemsarepreferredinsteadofaparallelbus,becauseofthesimplerwiring.Astheefficiencyofserialbusesincreases,thespeedadvantageoftheparalleldatatransmissiongetslessimportant.TheclockfrequenciesofSPIdevicescangouptosomeMegahertzandmore.Therearealotofapplicationwhereaserialtransmissionisperfectlysufficient.TheusageofSPIisnotlimitedtothemeasuringarea,alsointheaudiofieldthistypeoftransmissionisused.
TheSPI(thisnamewascreatedbyMotorola)isalsoknownasMicrowire,trademarkofNationalSemiconductor.Bothhavethesamefunctionality.TherearealsotheextensionsQSPI(QueuedSerialPeripheralInterface)andMicrowirePLUS.
ThepopularityofotherserialbussystemslikeI2C,CANbusorUSBshows,thatserialbusesgetusedmoreandmore.
BelowisalistofSPIdevices.Howeverthislistneitherclaimstobecompletenoristheavailablabilityofthelistedcomponentsguaranteed.InadditionthereisalistofmanufacturerswiththetypeofSPIcomponentstheyproduce.
MartinSchwerdtfeger,06/2000
ThePrinciple
TheSerialPeripheralInterfaceisusedprimarilyforasynchronousserialcommunicationofhostprocessorandperipherals.However,aconnectionoftwoprocessorsviaSPIisjustaswellpossibleandisdescribedattheendofthechapter.
Inthestandardconfigurationforaslavedevice(seeillustration1),twocontrolandtwodatalinesareused.ThedataoutputSDOservesontheonehandthereadingbackofdata,offershoweveralsothepossibilitytocascadeseveraldevices.ThedataoutputoftheprecedingdevicethenformsthedatainputforthenextIC.
Illustration1:
SPIslave
ThereisaMASTERandaSLAVEmode.TheMASTERdeviceprovidestheclocksignalanddeterminesthestateofthechipselectlines,i.e.itactivatestheSLAVEitwantstocommunicatewith.CSandSCKLarethereforeoutputs.
TheSLAVEdevicereceivestheclockandchipselectfromtheMASTER,CSandSCKLarethereforeinputs.
Thismeansthereisonemaster,whilethenumberofslavesisonlylimitedbythenumberofchipselects.
ASPIdevicecanbeasimpleshiftregisteruptoanindependentsubsystem.Thebasicprincipleofashiftregisterisalwayspresent.Commandcodesaswellasdatavaluesareseriallytransferred,pumpedintoashiftregisterandaretheninternallyavailableforparallelprocessing.Herewealreadyseeanimportantpoint,thatmustbeconsideredinthephilosophyofSPIbussystems:
Thelengthoftheshiftregistersisnotfixed,butcandifferfromdevicetodevice.Normallytheshiftregistersare8Bitorintegralmultiplesofit.Ofcoursetherealsoexistshiftregisterswithanoddnumberofbits.Forexampletwocascaded9BitEEPROMscanstore18Bitdata.
IfaSPIdeviceisnotselected,itsdataoutputgoesintoahigh-impedancestate(hi-Z),sothatitdoesnotinterferewiththecurrentlyactivateddevices.WhencascadingseveralSPIdevices,theyaretreatedasoneslaveandthereforeconnectedtothesamechipselect.
Thustherearetwomeaningfultypesofconnectionofmasterandslavedevices.illustration2showsthetypeofconnectionforcascadingseveraldevices.
Illustration2:
CascadingseveralSPIdevices
Inillustration2thecascadeddevicesareevidentlylookedatasonelargerdeviceandreceivethereforethesamechipselect.Thedataoutputoftheprecedingdeviceistiedtothedatainputofthenext,thusformingawidershiftregister.
Ifindependentslavesaretobeconnectedtoamasteranotherbusstructurehastobechosen,asshowninillustration3.Here,theclockandtheSDIdatalinesarebroughttoeachslave.AlsotheSDOdatalinesaretiedtogetherandledbacktothemaster.OnlythechipselectsareseparatelybroughttoeachSPIdevice.
Illustration3:
Masterwithindependentslaves
Lastnotleastbothtypesmaybecombined.
ItisalsopossibletoconnecttwomicrocontrollersviaSPI.Forsuchanetwork,twoprotocolvariantsarepossible.Inthefirst,thereisonlyonemasterandseveralslavesandinthesecond,eachmicrocontrollercantaketheroleofthemaster.Fortheselectionofslavesagaintwoversionswouldbepossiblebutonlyonevariantissupportedbyhardware.Thehardwaresupportedvariantiswiththechipselects,whileintheothertheselectionoftheslavesisdonebymeansofanIDpackedintotheframes.TheassignmentoftheIDsisdonebysoftware.Onlytheselectedslavedrivesitsoutput,allotherslavesareinhigh-impedancdstate.Theoutputremainsactiveaslongastheslaveisselectedbyitsaddress.
Thefirstvariant,namedsingle-masterprotocol,resemblesthenormalmaster-slavecommunication.Themicrocontrollerconfiguredasaslavebehaveslikeanormalperipheraldevice.
Thesecondpossibilityworkswithseveralmastersandisthereforenamedmulti-masterprotocol.Eachmicroprocessorhasthepossibilitytotaketherollofthemasterandtoaddressanothermicroprocessor.Onecontrollermustpermanentlyprovideaclocksignal.TheMC68HC11providesaharwareerrorrecognition,usefulinmultiple-mastersystems.TherearetwoSPIsystemerrors.ThefirstoccursifseveralSPIdeviceswanttobecomemasteratthesametime.TheotherisacollisionerrorthatoccursforexamplewhenSPIdevicesworkwithwithdifferentpolarities.MoredetailscanbefoundintheMC68HC11manual.
DataandControlLinesoftheSPI
TheSPIrequirestwocontrollines(CSandSCLK)andtwodatalines(SDIandSDO).MotorolanamestheselinesMOSI(Master-Out-Slave-In)andMISO(Master-In-Slave-Out).ThechipselectlineisnamedSS(Slave-Select).
WithCS(Chip-Select)thecorrespondingperipheraldeviceisselected.Thispinismostlyactive-low.IntheunselectedstatetheSDOlinesarehi-Zandthereforeinactive.Themasterdecideswithwhichperipheraldeviceitwantstocommunicate.TheclocklineSCLKisbroughttothedevicewhetheritisselectedornot.Theclockservesassynchronizationofthedatacommunication.
ThemajorityofSPIdevicesprovidethesefourlines.SometimesithappensthatSDIandSDOaremultiplexed,forexampleinthetemperaturesensorLM74fromNationalSemiconductor,orthatoneoftheselinesismissing.Aperipheraldevicewhichmustorcannotbeconfigured,requiresnoinputline,onlyadataoutput.Assoonasitgetsselecteditstartssendingdata.InsomeADCsthereforetheSDIlineismissing(e.g.MCCP3001fromMicrochip).
Therearealsodevicesthathavenodataoutput.ForexampleLCDcontrollers(e.g.COP472-3fromNationalSemiconductor),whichcanbeconfigured,butcannotsenddataorstatusmessages.
SPIConfiguration
Becausethereisnoofficialspecification,whatexactlySPIisandwhatnot,itisnecessarytoconsultthedatasheetsofthe