pld运用程序举例.docx
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pld运用程序举例
PLD段码显示
libraryieee;
useieee.std_logic_1164.all;
entityduanmais
port(fff:
outbit_vector(1to5);
aaa:
outbit_vector(1to5));
end;
architecturekkofduanmais
begin
fff(1to5)<="11111";
aaa(1to5)<="11111";
end;
PLD三个数加法编程
libraryieee;
useieee.std_logic_1164.all;
entityjwis
port(in1,in2:
inintegerrange0to15;
a,b:
outstd_logic_vector(1to7));
end;
architectureggofjwis
signalhe:
integerrange0to45;
begin
he<=in1+in2;
withheselect
a<="1111110"when0|10|20|30|40,
"0110000"when1|11|21|31|41,
"1101101"when2|12|22|32|42,
"1111001"when3|13|23|33|43,
"0110011"when4|14|24|34|44,
"1011011"when5|15|25|35|45,
"1011111"when6|16|26|36,
"1110000"when7|17|27|37,
"1111111"when8|18|28|38,
"1111011"when9|19|29|39,
"0000000"whenothers;
withheselect
b<="0000000"when0<=heandhe<=9,else
"0110000"when10<=heandhe<=19,else
"1101101"when20<=heandhe<=29,else
"1111001"when30<=heandhe<=39,else
"0110011"when40<=heandhe<=39,else
"0000000"whenothers;
end;
PLD八个按键两个灯
libraryieee;
useieee.std_logic_1164.all;
entityguozi3is
port(in1,in2:
instd_logic_vector(1to4);
a,b:
outstd_logic_vector(1to8));
end;
architectureggofguozi3is
begin
within1select
"0110000"when"0001",
"1101101"when"0010",
"1111001"when"0011",
"0110011"when"0100",
"1011011"when"0101",
"1011111"when"0110",
"1110000"when"0111",
"1111111"when"1000",
"1111011"when"1001",
"0000000"whenothers;
within2select
b<="0110000"when"0001",
"1101101"when"0010",
"1111001"when"0011",
"0110011"when"0100",
"1011011"when"0101",
"1011111"when"0110",
"1110000"when"0111",
"1111111"when"1000",
"1111011"when"1001",
"0000000"whenothers;
end;
PLD顺序语句编程(0加到9)
libraryieee;
useieee.std_logic_1164.all;
entityjinchenis
port(in1:
instd_logic;
a:
outstd_logic_vector(1to7));
end;
architectureggofjinchenis
signalss:
integerrange0to9;
begin
process
begin
waituntilin1='1';
ss<=ss+1;
ifss=10then
ss<=0;
endif;
endprocess;
withssselect
a<="1111110"when0,
"0110000"when1,
"1101101"when2,
"1111001"when3,
"0110011"when4,
"1011011"when5,
"1011111"when6,
"1110000"when7,
"1111111"when8,
"1111011"when9,
"0000000"whenothers;
end;
PLD矢量10个控制2个数码管
libraryieee;
useieee.std_logic_1164.all;
entity kongzhi2is
port(a:
outbit_vector(1to7);
b:
in bit_vector(1to10));
end;
architectureffofkongzhi2is
begin
a<="1111110"when b="1000000000"else
"0110000"when b="0100000000"else
"1101101"when b="0010000000"else
"1111001"when b="1001000000"else
"0110011"when b="1000100000"else
"1011011"when b="1000010000"else
"1011111"when b="1000001000"else
"1110000"when b="1000000100"else
"1111111"when b="1000000010"else
"1110011"when b="1000000001"else
"0000000";
end;
PLD晶振50M控制数码管
libraryieee;
useieee.std_logic_1164.all;
entityjinzhengis
port(in50m:
instd_logic;
a:
outstd_logic_vector(1to7));
end;
architectureggofjinzhengis
signalin1:
std_logic;
signalss:
integerrange0to9;
signalcount:
integerrange0to25000000;
begin
process
begin
waituntilin50m='1';
count<=count+1;
ifcount=25000000then
count<=0;
in1<=notin1;
endif;
endprocess;
process
begin
waituntilin1='1';
ss<=ss+1;
ifss=10then
ss<=0;
endif;
endprocess;
withssselect
a<="1111110"when0,
"0110000"when1,
"1101101"when2,
"1111001"when3,
"0110011"when4,
"1011011"when5,
"1011111"when6,
"1110000"when7,
"1111111"when8,
"1111011"when9,
"0000000"whenothers;
end;
PLD晶振50M自动跳变程序(0到59)
libraryieee;
useieee.std_logic_1164.all;
entityjiadxxis
port(in50m:
instd_logic;
a,b:
outstd_logic_vector(1to7));
end;
architectureggofjiadxxis
signalin1:
std_logic;
signalt,g:
integerrange0to9;
signalcount:
integerrange0to5925000000;
begin
process
begin
waituntilin50m='1';
count<=count+1;
ifcount=25000000then
count<=0;
in1<=notin1;
endif;
endprocess;
process
begin
waituntilin1='1';
g<=g+1;
ifg=9thenifg=5then改变变量
g<=0;
t<=t+1;
ift=5then
t<=0;
endif;
endif;
endprocess;
withgselect
a<="1111110"when0,
"0110000"when1,
"1101101"when2,
"1111001"when3,
"0110011"when4,
"1011011"when5,
"1011111"when6,
"1110000"when7,
"1111111"when8,
"1111011"when9,
"0000000"whenothers;
withtselect
b<="1111110"when0,
"0110000"when1,
"1101101"when2,
"1111001"when3,
"0110011"when4,
"1011011"when5,
"1011111"when6,
"1110000"when7,
"1111111"when8,
"1111011"when9,
"0000000"whenothers;
end;
PLD(1-8数码管显示)第六个显示0
libraryieee;
useieee.std_logic_1164.all;
entityjiadxxis
port(a:
outstd_logic_vector(1to7);
b:
outstd_logic_vector(1to3));
end;
architecturekkofjiadxxis
begin
a<="1111110"