基带板原理图设计文档Word格式文档下载.docx
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与FPGA相连,用于交换控制信息;
McBSP0:
用于CODIC
McBSP1:
与FPGA相连,用于交换数据信息;
RapidIO:
用于与FPGA和ARM之间产生硬件中断;
FPGA:
完成系统定时、射频数据的接收及部分物理层算法;
PCI:
用于与射频交换数据,需要确认。
4、时钟设计
LET要求的采样时钟:
122.88MHz
ARM工作时钟:
12MHz,可以通过外部的晶振提供或外部的时钟提供;
27MHz,用于其中的某些模块,可以选择是否使能;
32.768KHz,看门狗时钟;
DSP工作时钟:
CLKIN1:
33.3~66.6MHz选50MHz
CLKIN2:
12.5~26.7MHz选25MHz
EMIFCLK:
160或200MHz选200MHz
SRIOCLK:
125或156.25或312.5MHz选择125MHz备156.25MHz
系统时钟为20MHz,通过TI的CDCE937产生DSP和ARM的输入时钟
OUT
Freq
Y1
20MHz
ToFPGA
Y2
25MHz
DSPPLL1
Y3
125MHz
SRIO
Y4
50MHz
DSPPLL2
Y5
200MHz
DSP_EMIFA
Y6
12MHz
ARM
Y7
48MHz
Y8
122.88MHz
LTEtoFPGA
Y9
考虑到板子单独使用和与41所接口使用的情况:
单独使用安上述设置使用
与41所接口使用时,系统时钟由41所射频板提供,时钟为122.88MHz,经过CPLD分频后得到15.36MHz的时钟,再输出到CDCE946后产生相应的其他时钟,输入为:
125或156.25或312.5MHz选择125MHz备156.25MHz
5电源设计
需求:
6410
电源种类:
1.2、1.8V、2.5V、3.3V
Signal
I/O
Description
Voltage
推荐值
选择值
VDDALIVE
P
Internalpowerforaliveblock
1.2
1.2
VDDARM
InternalpowerforARM1176coreandcache
1.1/1.2
VDDINT
Internalpowerforlogic
VDDMPLL
PowerforMPLLcore
VDDAPLL
PowerforAPLLcore
VDDEPLL
PowerforEPLLcore
VDDOTG
PowerforUSBOTGPHY
3.3
3.3
VDDOTGI
InternalpowerforUSBOTGPHY
VDDMMC
IOpowerforSDMMC
1.8~3.3
VDDHI
IOpowerforHostI/F
VDDLCD
IOpowerforLCD
VDDPCM
IOpowerforPCM(AudioI/F−I2S,AC97)
VDDEXT
IOpowerforexternalI/F(UART,I2C,CameraI/F,etc.)
VDDSYS
IOpowerforsystemcontrol.(Clock,reset,operationmode,JTAG,etc)
VDDUH
PowerforUSBHost
VDDADC
PowerforADCcoreandIO
VDDDAC
PowerforDACcoreandIO
VDDRTC
PowerforRTClogicandIO
1.8~3.0
2.5
VDDM0
IOpowerforMemoryPort0
VDDSS
IOpowerforATAIOmuxedinMEM0port
VDDM1
IOpowerforMemoryPort1
1.8/2.5
1.8
6455
1.2v、1.8v、3.3v
VREFSSTL
A
(DVDD18/2)-VreferenceforSSTLbuffer(DDR2MemoryController).Thisinput
voltagecanbegenerateddirectlyfromDVDD18usingtwo1-kΩresistorstoform
aresistordividercircuit.
1.8V/2
VREFHSTL
(DVDD15/2)-VreferenceforHSTLbuffer(EMACRGMII).VREFHSTLcanbe
generateddirectlyfromDVDD15usingtwo1-kΩresistorstoformaresistor
dividercircuit.
1.5V/2
DVDDR
S
1.8-VI/Osupplyvoltage.(SRIOregulatorsupply)
1.8V
AVDDA
SRIOanalogsupply:
1.25-VI/Osupplyvoltage(-1000and-1200devices)
1.2-VI/Osupplyvoltage(-850and-720devices).
Donotusecoresupply.
1.25V
1.2V
AVDLL1
1.8-VI/Osupplyvoltage.
AVDLL2
DVDDRM
SRIOinterfacesupply:
1.25-Vcoresupplyvoltage(-1000and-1200devices)
1.2-Vcoresupplyvoltage(-850and-720devices).
thesourceforthissupplyvoltagemustbethesameasthatofCVDD
DVDD12
MainSRIOsupply:
AVDDT
SRIOterminationsupply:
1.25-VI/Osupplyvoltage(-1000and-1200devices).
DVDD15
1.8-Vor1.5-VI/OsupplyvoltagefortheRGMIIfunctionoftheEMAC.
1.5V
DVDD18
1.8-VI/Osupplyvoltage(DDR2MemoryController)
DVDD33
3.3-VI/Osupplyvoltage
3.3V
CVDD
1.25-Vcoresupplyvoltage(-1000and-1200devices).
FPGA
VCCAUX
VCCINT
1.0
VCCO
电源选择:
FPGA:
3A
TPS74401
10A
PTH04T240W
6A
PTH08T230W/TPS51100
DSP、ARM
TPS65051
PTH08T230W
1.25
6、FPGA模式选择:
ConfigurationMode
M[2:
0]
BusWidth
CCLKDirection
MasterSerial
000
1
Output
MasterSPI
001
MasterBPI-Up
8,16
MasterBPI-Down
011
MasterSelectMAP
100
JTAG
101
Input(TCK)
SlaveSelectMAP
110
8,16,32
Input
SlaveSerial
111
我们系统中选择JTAG或SlaveSelectMAP,所以M2固定为高,M[1:
0]为01则为JTAG,为10即为SlaveSelectMAP,为11则为slaveserial
SlaveSelectMAP模式下:
可以设置为DSPboot还是armboot,
需要的信号:
CCLK:
写使能
CS_B:
片选
RDWR_B:
GPIO
slaveserial模式下:
GPIO
D_IN:
7、DSP设置:
AEA19/BOOTMODE3
AEA18/BOOTMODE2
AEA17/BOOTMODE1
AEA16/BOOTMODE0
设置
Boot模式:
0000-Noboot(defaultmode)
0001-Hostboot(HPI)
0010-Reserved
0011-Reserved
0100-EMIFA8-bitROMboot
0101-MasterI2Cboot
0110-SlaveI2Cboot
0111-Hostboot(PCI)
1000thru1111-SerialRapidI/Obootconfigurations
CFGGP[2:
0]pinsmustbesetto000bduringresetforproperoperationofthePCIbootmode.
AEA15/AECLKIN_SEL
EMIFA输入时钟选择
0-AECLKIN(defaultmode)
1-SYSCLK4(CPU/x)ClockRate.TheSYSCLK4clockrateissoftwareselectableviatheSoftwarePLL1Controller.Bydefault,SYSCLK4is
selectedasCPU/8clockrate.
AEA14/HPI_WIDTH
1
HPI总线宽度选择
0-HPIoperatesasanHPI16(default).(HPIbusis16bitswide.HD[15:
0]
pinsareusedandtheremainingHD[31:
16]pinsarereservedpinsinthe
Hi-Zstate.)
1-HPIoperatesasanHPI32.
AEA13/LENDIAN
DeviceEndianmode(LENDIAN)
0-SystemoperatesinBigEndianmode
1-SystemoperatesinLittleEndianmode(default)
AEA12/UTOPIA_EN
UTOPIAEnablebit(UTOPIA_EN)
UTOPIAperipheralenable(functional)
0-UTOPIAdisabled;
EthernetMAC(EMAC)andMDIOenable(default).
EMAC/MDIOconfiguration(interface)[MII,RMII,GMIIorthestandaloneRGMII]iscontrolledbytheMACSEL[1:
0]bits.
1-UTOPIAenabled;
EMACandMDIOdisabled[exceptwhentheMACSEL[1:
0]bits=11then,theEMAC/MDIORGMIIinterfaceisstillfunctional].
AndifMACSEL[1:
0]=11,theRGMIIstandalonepinfunctionscanbeused.
AEA11
必须接1k下拉电阻
AEA10/MACSEL1
AEA9/MACSEL0
EMAC/MDIOinterfaceselectbits
AEA8/PCI_EEAI
AEA8:
PCIauto-initializationviaexternalI2CEEPROM
IfthePCIperipheralisdisabled(PCI_ENpin=0),thispinmustnotbe
pulledup.
0-PCIauto-initializationthroughI2CEEPROMisdisabled(default).
1-PCIauto-initializationthroughI2CEEPROMisenabled.
AEA7
AEA6/PCI66
PCIFrequencySelection(PCI66)
0-PCIoperatesat33MHz(default).
1-PCIoperatesat66MHz.
IfthePCIperipheralisdisabled(PCI_EN=0),thispinmustnotbe
AEA5/MCBSP1_EN
McBSP1Enablebit(MCBSP1_EN)
0-GPIOpinfunctionsenabled(default).
1-McBSP1pinfunctionsenabled.
ASEYAS4C/LKOUT_EN
SYSCLKOUTEnablepin(SYSCLKOUT_EN)
0-GP[1]pinfunctionoftheSYSCLK4/GP[1]pinenabled(default).
1-SYSCLK4pinfunctionoftheSYSCLK4/GP[1]pinenabled.
AEA3
SRIO使能:
上拉
SRIO不使能:
下拉
AEA2/CFGGP2
AEA1/CFGGP1
AEA0/CFGGP0
000
ConfigurationGPI(CFGGP[2:
0])(AEA[2:
0])
Thesepinsarelatchedduringresetandtheirvaluesareshowninthe
DEVSTATregister.Thesevaluescanbeusedbysoftwareroutinesforboot
operations.
ABA1/EMIFA_EN
使能
ABA0/DDR2_EN
左
DSP_EMIFA_BA0
DDR2_EN
DSP_EMIFA_ADD19
BOOTMODE3
DSP_EMIFA_ADD8
PCI_EEAI
右
DSP_EMIFA_ADD17
BOOTMODE1
S12
DSP_EMIFA_ADD18
BOOTMODE2
DSP_EMIFA_ADD15
AECLKIN_SEL
DSP_EMIFA_ADD14
HPI_WIDTH
DSP_EMIFA_ADD13
LENDIAN
DSP_EMIFA_ADD12
UTOPIA_EN
DSP_EMIFA_ADD11
DSP_EMIFA_ADD10
MACSEL1
DSP_EMIFA_ADD9
MACSEL0
DSP_EMIFA_ADD7
S9/S11
DSP_EMIFA_ADD6
PCI66
DSP_EMIFA_ADD16
BOOTMODE0
DSP_EMIFA_ADD5
MCBSP1_EN
DSP_EMIFA_ADD4
SYSCLKOUTEn
DSP_EMIFA_ADD3
SRIO使能
DSP_EMIFA_ADD2
CFGGP2
DSP_EMIFA_ADD1
CFGGP1
DSP_EMIFA_ADD0
CFGGP0
DSP_EMIFA_BA1
EMIFA_EN
S8/S10