armok01134756文档格式.docx

armok01134756文档格式.docx

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∙Inputbandwidthis100MHz（typical）.

∙Highimpedanceinput,sothatitcanbeusedwithregularoscilloscopeprobes.

∙CompatiblewithdifferentHFconnectors（BNC,SMA,F,RCA）.

∙V-posandV-rangeadjustedwithpotentiometers,orDACs,dependingoftheFlashyrevision.

∙Typicalinputstagerangeof-5Vto+10Vwhenusingregular10:

1oscilloscopeprobes,goodforprobingdigitallogicsignalorsimilarlowvoltageapplications.

∙Uses3.3Vpower,3.3VIOs,0.1"

spacingconnector.

ForthelatestFlashydatasheet,seehere.

Flashyblockdiagram

stheblockdiagramofatypicalFlashyboard.

Theinputsignalontheleftisanalog,whiletheoutputsignalsontherightaredigital.

Theinputsignal（comingfromanoscilloscopeprobeforexample）isadjustedbythepre-amplifiertobecompatiblewiththeADC.TheADCdigitizesthesignalandcreatesthe8-bits100MSPSoutput.TheADCisclockedfroma100MHzlocaloscillator.The100MHzclocksignalisalsomadeavailableoutsideFlashy,sothatthe8-bitsoutputbuscanbesynchronouslycaptured（typicallybyanFPGAboard）.

TheV-posandV-rangecontrolsallowmovingthesignalupordown（verticalscale）.Asforthehorizontalscale,theADCisalwaysclockedat100MHz.Ifadifferenttimebaseisdesired,anFPGAattachedtoFlashyimplementsaFIRtodownsamplethedata.

Theperiodoutputisgeneratedbythepre-amplifier.ItallowstheFPGAtomeasurethefrequencyoftheinputsignal,whichcanbeusedtoreconstructperiodicsignals（"

equivalent-timesampling"

oscilloscopemode）.

FlashyandFlashyD

Flashyisavailablein2versions:

Flashy（oneinput）andFlashyD（twoinputs）.

stheblockdiagramofatypicalFlashyD（twoinputs）board.

FlashyandFPGAboards

Flashy/FlashyDarecompatiblewithalltheboards.The3.3VdigitalsignalsarecompatiblewithotherFPGAboardsaswell.

sthefpga4funboardscompatibilitytable:

Pluto

Pluto-II

Pluto-3

Pluto-P

Saxo/Xylo/Xylo-EM

Dragon

compatiblewith

Flashy

Flashy

FlashyD

FlashyD

TheboardsthatacceptFlashyDcanalsoacceptFlashy（FlashypinoutisasubsetofFlashyD）.

Flashyrevisions

Flashyexistsindifferentrevisions,eachwithitsownfeatureset.

ThispageisforFlashy"

Rev.Dandabove"

-seetheolderFlashypagehere.

FlashyrevisionD

Thisrevisionaddspotentiometerstoadjusttheinputstagevoltagelevels,aswellasthesensibilityoftheperiodoutput.

FlashyrevisionH

Thisrevisionaddsanoptionaljumpertohelptemporarilydisablingthelocaloscillator.

FlashyrevisionJ

ThisrevisionreplacestheV-posandV-rangepotentiometersbyDACs,controlledfromtheFPGA.Thatmakestheboardplug-and-play（nopotentiometerstoadjustanymore）.

stherev.Jblockdiagram.

WheretobuyFlashy?

FlashyisavailableforsaleontheKNJN.comwebsite.

Flashysoftware

FormoredetailsabouttheHDL/softwaredesign,seethedigitaloscilloscopeproject.

Links

∙InformationaboutRFconnectorsonAmphenolRFsite.

∙PicturesofthemostcommonHFconnectorsonthisCommonMicrowavecableconnectorspage.

Digitaloscilloscope

YoucanbuildadigitaloscilloscopesimplybyhookinganADCandanFPGAtogether.

Thisparticulardesignusesan100MHzflashADC,sowearebuildingan100MSPS（mega-samples-per-seconds）oscilloscope.

Adigitaloscilloscopehasmanyadvantagesoveritsanalogcounterpart,liketheabilitytocapturesingleevents,andtodisplaywhathappensbeforethetrigger.

ThisoscilloscopedesignisinterestingbecauseitshowshowpowerfulandusefulmodernFPGAscanbe.ButifyouarenewtoFPGAtechnology,keepthatinmindthisisnottheeasiestdesigntounderstandonthissite.

Finally,notethatadigitaloscilloscopeisverysimilartoalogicanalyzer.Botharestoragedevices.SimplyremovetheADCandfeeddirectlytheFPGA.Maybetheobjectofafutureproject?

HDLdesign

∙HDLpart1-FIFO-baseddesign.

∙HDLpart2-RAM-baseddesign.

∙HDLpart3-Triggermechanism.

∙HDLpart4-Morefunctionality.

Electronicdesign:

seetheFlashyboard.

Software

∙Softwarefeaturesandscreenshots.

∙Seealsointerferencepatterns.

Screenshot

stheviewofa27MHzsignal,sampledat100MHzandreconstructedusingthe"

sampleequivalenttime"

technique.

∙HowtobuildadigitaloscilloscopebasedontheADC0804andOpenGL

∙AniceOscilloscopeFAQsitewithlotsofinformation.

∙Howoscilloscopeswork