DDR3verilog代码Word格式文档下载.docx
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tcheckforaveragerefreshtimings
*-positiveckandck_nedgesareusedtoforminternalclock
*-positivedqsanddqs_nedgesareusedtolatchdata
*-testmodeisnotmodeled
*-DutyCycleCorrectorisnotmodeled
*-TemperatureCompensatedSelfRefreshisnotmodeled
*-DLLoffmodeisnotmodeled.
*Note:
-Setsimulatorresolutionto"
ps"
accuracy
*-SetDEBUG=0todisable$displaymessages
*DisclaimerThissoftwarecodeandallassociateddocumentation,commentsorother
*ofWarranty:
information（collectively"
Software"
）isprovided"
ASIS"
without
*warrantyofanykind.MICRONTECHNOLOGY,INC.（"
MTI"
）EXPRESSLY
*DISCLAIMSALLWARRANTIESEXPRESSORIMPLIED,INCLUDINGBUTNOTLIMITED
*TO,NONINFRINGEMENTOFTHIRDPARTYRIGHTS,ANDANYIMPLIEDWARRANTIES
*OFMERCHANTABILITYORFITNESSFORANYPARTICULARPURPOSE.MTIDOESNOT
*WARRANTTHATTHESOFTWAREWILLMEETYOURREQUIREMENTS,ORTHATTHE
*OPERATIONOFTHESOFTWAREWILLBEUNINTERRUPTEDORERROR-FREE.
*FURTHERMORE,MTIDOESNOTMAKEANYREPRESENTATIONSREGARDINGTHEUSEOR
*THERESULTSOFTHEUSEOFTHESOFTWAREINTERMSOFITSCORRECTNESS,
*ACCURACY,RELIABILITY,OROTHERWISE.THEENTIRERISKARISINGOUTOFUSE
*ORPERFORMANCEOFTHESOFTWAREREMAINSWITHYOU.INNOEVENTSHALLMTI,
*ITSAFFILIATEDCOMPANIESORTHEIRSUPPLIERSBELIABLEFORANYDIRECT,
*INDIRECT,CONSEQUENTIAL,INCIDENTAL,ORSPECIALDAMAGES（INCLUDING,
*WITHOUTLIMITATION,DAMAGESFORLOSSOFPROFITS,BUSINESSINTERRUPTION,
*ORLOSSOFINFORMATION）ARISINGOUTOFYOURUSEOFORINABILITYTOUSE
*THESOFTWARE,EVENIFMTIHASBEENADVISEDOFTHEPOSSIBILITYOFSUCH
*DAMAGES.Becausesomejurisdictionsprohibittheexclusionor
*limitationofliabilityforconsequentialorincidentaldamages,the
*abovelimitationmaynotapplytoyou.
*Copyright2003MicronTechnology,Inc.Allrightsreserved.
*RevAuthorDateChanges
*---------------------------------------------------------------------------------------
*0.41JMK05/12/06Removedauto-prechargetopowerdownerrorcheck.
*0.42JMK08/25/06Createdinternalclockusingckandck_n.
*TDQScanonlybeenabledinEMRforx8configurations.
*CASlatencyischeckedvsfrequencywhenDLLlocks.
*ImprovedcheckingofDQSduringwrites.
*AddedtrueBL4operation.
*0.43JMK08/14/06AddedcheckingforsettingreservedbitsinModeRegisters.
*AddedODTSReadout.
*ReplacedtZQCLwithtZQinitandtZQoper
*FixedtWRPDENandtWRAPDENduringBC4MRSandBL4MRS.
*AddedtRFCcheckingforRefreshtoPower-DownRe-Entry.
*AddedtXPDLLcheckingforPower-DownExittoRefreshtoPower-DownEntry
*AddedClockFrequencyChangeduringPrechargePower-Down.
*Added-125xspeedgrades.
*FixedtRCDcheckingduringWrite.
*1.00JMK05/11/07Initialrelease
*1.10JMK06/26/07FixedODTH8checkduringBLOTF
*RemovedtempsensorreadoutfromMPR
*Updatedinitializationsequence
*Updatedtimingparameters
*1.20JMK09/05/07Updatedclockfrequencychange
*Addedddr3_dimmmodule
*1.30JMK01/23/08Updatedtimingparameters
*1.40JMK12/02/08AddedsupportforDDR3-1866andDDR3-2133
*renamedddr3_dimm.vtoddr3_module.vandaddedSODIMMsupport.
*Addedmulti-chippackagemodelsupportinddr3_mcp.v
*1.50JMK05/04/08Added1866and2133speedgrades.
*1.60MYY07/10/09Mergingof1.50versionandpre-1.0versionchanges
*1.61SPH12/10/09OnlychecktIHforcmd_addrifCS#LOW
*****************************************************************************************/
//DONOTCHANGETHETIMESCALE
//MAKESUREYOURSIMULATORUSES"
PS"
RESOLUTION
`timescale1ps/1ps
//modelflags
//`defineMODEL_PASR
moduleddr3（
rst_n,
ck,//
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_tdqs,
ba,
addr,
dq,
dqs,
dqs_n,
tdqs_n,//
odt
）;
`include"
ddr3_parameters.vh"
parametercheck_strict_mrbits=1;
parametercheck_strict_timing=1;
parameterfeature_pasr=1;
parameterfeature_truebl4=0;
//textmacros
`defineDQ_PER_DQSDQ_BITS/DQS_BITS
`defineBANKS（1<
<
BA_BITS）
`defineMAX_BITS（BA_BITS+ROW_BITS+COL_BITS-BL_BITS）
`defineMAX_SIZE（1<
（BA_BITS+ROW_BITS+COL_BITS-BL_BITS））
`defineMEM_SIZE（1<
MEM_BITS）
`defineMAX_PIPE4*CL_MAX
//DeclarePorts
inputrst_n;
inputck;
inputck_n;
inputcke;
inputcs_n;
inputras_n;
inputcas_n;
inputwe_n;
inout[DM_BITS-1:
0]dm_tdqs;
input[BA_BITS-1:
0]ba;
input[ADDR_BITS-1:
0]addr;
inout[DQ_BITS-1:
0]dq;
inout[DQS_BITS-1:
0]dqs;
0]dqs_n;
output[DQS_BITS-1:
0]tdqs_n;
inputodt;
/
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