数字电路与逻辑设计11.ppt
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,DigitalFundamentalsTenthEditionFloyd,Chapter11,Summary,ProgrammableLogic,SPLD:
(SimplePLDs)aretheearliesttypeofarraylogicusedforfixedfunctionsandsmallercircuitswithalimitednumberofgates.(ThePALandGALarebothSPLDs).CPLD:
(ComplexPLDs)aremultipleSPLDsarraysandinter-connectionarraysonasinglechip.FPLD:
(FieldProgrammableGateArray)areamoreflexiblearrangementthanCPLDs,withmuchlargercapacity.,ProgrammableLogicDevices(PLDs)areICswithalargenumberofgatesandflipflopsthatcanbeconfiguredwithbasicsoftwaretoperformaspecificlogicfunctionorperformthelogicforacomplexcircuit.MajortypesofPLDsare:
Summary,ProgrammableLogic,AdvantagestoPLDsinclude,ReducedcomplexityofcircuitboardsLowerpowerrequirementsLessboardspaceSimplertestingproceduresHigherreliabilityDesignflexibility,Summary,PALsandGALs,PALshaveaonetimeprogrammable(OTP)array,inwhichfusesarepermanentlyblown,creatingtheproducttermsinanANDarray.,AllPLDscontainarrays.TwoimportantSPLDsarePALs(ProgrammableArrayLogic)andGALs(GenericArrayLogic).AtypicalarrayconsistsofamatrixofconductorsconnectedinrowsandcolumnstoANDgates.,SimplifiedAND-ORarray,X,AABB,Summary,X,AABB,Whatfunctionisrepresentedbythearray?
Example,Solution,ThefunctionrepresentsanXORgate.,X=AB+AB,PALsareprogrammedwithaspecializedprogrammerthatblowsselectedinternalfuselinks.Afterblowingthefuses,thearrayrepresentstheBooleanlogicexpressionforthedesiredcircuit.,PALsandGALs,Summary,TheGAL(GenericArrayLogic)issimilartoaPALbutcanbereprogrammed.Forthisreason,theyareusefulfornewproductdevelopment(prototyping)andfortrainingpurposes.,AABB,X,GALsweredevelopedbyLatticeSemiconductor.Theyarehighspeed,extremelyfastdevicesandcaninterfacewithboth3.3Vor5Vlogicsignals.,PALsandGALs,Summary,PALsandGALscanberepresentedwithasimplifieddiagram.Asinglelinecanrepresentmultiplegateinputs.ThelogicshownisfortheXORgate,givenpreviously.,Inputbuffer,AABB,SinglelinewithslashindicatingmultipleANDgateinputs,Fuseblown,Fuseintact,AB,AB,AB+AB,PALsandGALs,Summary,PALsandGALshavelargearraylogicandincludeoutputlogicthatvariesincomplexity.TheoutputlogicisconnectedtoeachORgateandtogetherisreferredtoasamacrocell.TwotypesofPAL/GALmacrocellsareshown.Fortheseparticularmacrocells,theI/Opinscanserveasaninputoranoutput.,Tristatecontrol,FromANDarray,FromANDarray,I/O,I/O,Programmablefuselinktocontroloutputpolarity,ToANDarray,ToANDarray,PALsandGALs,Summary,ThePAL16V8isatypicalSPLD.Thereare16pinsthatcanbeusedasinputsand8pinsthatcanbeusedasoutputs.I/Opinsarecountedasbothinputsandoutputs.,I1,I2,I3,I4,I5,I6,I7,I8,I9,I/O10,O1,I/O1,I/O2,I/O3,I/O4,I/O5,I/O6,O2,ProgrammableANDarray,PLCCPackage,PALsandGALs,Summary,CPLDs,Acomplexprogrammablelogicdevice(CPLD)hasmultiplelogicarrayblocks(LABs)thatareactuallySPLDsonasingleIC.LABsareconnectedviaaprogrammableinterconnectarray(PIA).VariousCPLDshavedifferentstructuresfortheseelements.,ThePIAistheinterconnectionbetweentheLABs.LogicisfittedtotheCPLDandroutingisdeterminedbyahigh-levelprogramminglanguagecalledahardwaredescriptionlanguage(HDL).,Summary,CPLDs,ThearchitectureofaCPLDisthewayinwhichtheinternalelementsareconfigured.AportionoftheAlteraMAX7000seriesisshown.ThisstructureistypicalforCPLDsalthoughdensities,size,speed,andinternalfactors(macrocells,etc)willvarybetweenmanufacturers.,I/Opins,I/Opins,General-purposeinputs,Summary,CPLDs,MacrocellsintheAlteraMAX7000seriescangenerateuptofiveproductterms.Forexpressionsrequiringmoreterms,theoutputcanbeexpandedasdescribedinthetext.,Summary,Macrocells,Inadditiontocombinationlogic,somemacrocellshaveregisteredoutputsavailable(usingprogrammableflip-flops).ThisallowstheCPLDtoperformsequentiallogic.,Summary,FPGAs,Afieldprogrammablegatearray(FPGA)usesadifferentarchitecturethanaCPLD.Theconfigurablelogicblock(CLB)isthebasicelementwhichisreplicatedmanytimes.,CLBsarearrangedinarowandcolumnstructure.WithintheCLBsarelogicmodulesjoinedbylocalinterconnects.Generally,thelogicmodulesarecomposedofalook-uptable(LUT),aflip-flop,andaMUXthatcanbeusedtobypasstheflip-flopforstrictlycombinationallogic.,Summary,FPGAs,Logicmodulescanbeconfiguredforcombinationallogic,registeredlogic,oracombinationofboth.Theglobalinterconnectsdistributesignals(includingtheclock)tovariousCLBs.,FPGAsmayalsohaveahardcoreportionoflogicthatisputinbythemanufacturerandcannotbereprogrammedbytheuser.TheseFPGAsareusefulincommonlyusedfunctionssuchasI/Ointerfaces.,Summary,ProgrammableLogicSoftware,Allmanufacturersofprogra