数字电子技术(Floyd 第十版)课件Chapter -07-st.ppt
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,DigitalFundamentalsTenthEditionFloyd,Chapter7,2008PearsonEducation,CombinationalcircuitvsSequentialcircuit,組合電路(Combinationalcircuit)並不會儲存之前發生過的狀態循序電路(Sequentialcircuit)會根據目前的狀態來決定下一次的輸出狀態,Alatchisatemporarystoragedevicethathastwostablestates(bistable).Itisabasicformofmemory.,Summary,Latches,TheS-R(Set-Reset)latchisthemostbasictype.ItcanbeconstructedfromNORgatesorNANDgates.WithNORgates,thelatchrespondstoactive-HIGHinputs;withNANDgates,itrespondstoactive-LOWinputs.,NORActive-HIGHLatchNANDActive-LOWLatch,R,S,Q,Q,Theactive-HIGHS-Rlatchisinastable(latched)conditionwhenbothinputsareLOW.,Summary,Latches,AssumethelatchisinitiallyRESET(Q=0)andtheinputsareattheirinactivelevel(0).ToSETthelatch(Q=1),amomentaryHIGHsignalisappliedtotheSinputwhiletheRremainsLOW.,0,1,0,1,0,0,ToRESETthelatch(Q=0),amomentaryHIGHsignalisappliedtotheRinputwhiletheSremainsLOW.,0,0,1,0,1,0,LatchinitiallyRESET,LatchinitiallySET,Theactive-LOWS-Rlatchisinastable(latched)conditionwhenbothinputsareHIGH.,Summary,Latches,Q,1,1,0,1,0,1,LatchinitiallyRESET,Q,1,1,0,1,0,1,LatchinitiallySET,Neverapplyanactivesetandresetatthesametime(invalid).,Theactive-LOWS-Rlatchisavailableasthe74LS279AIC.,Summary,Latches,1Q,2Q,3Q,4Q,74LS279A,彈跳電路,Agatedlatchisavariationonthebasiclatch.,Summary,Latches,Thegatedlatchhasanadditionalinput,calledenable(EN)thatmustbeHIGHinorderforthelatchtorespondtotheSandRinputs.,R,S,Q,EN,ShowtheQoutputwithrelationtotheinputsignals.AssumeQstartsLOW.,Example,Solution,KeepinmindthatSandRareonlyactivewhenENisHIGH.,S,R,EN,Q,Summary,Latches,TheDlatchisanvariationoftheS-RlatchbutcombinestheSandRinputsintoasingleDinputasshown:
AsimplerulefortheDlatchis:
QfollowsDwhentheEnableisactive.,D,EN,Q,Q,D,EN,Summary,Latches,ThetruthtablefortheDlatchsummarizesitsoperation.IfENisLOW,thenthereisnochangeintheoutputanditislatched.,Summary,Latches,DeterminetheQoutputfortheDlatch,giventheinputsshown.,Q,D,EN,Example,Latchvsflip-flop,latch和flip-flop都是常用的記憶裝置,它們都擁有1個或2個穩定的輸出狀態,以及有1或2個輸入端可改變狀態。
latch則沒有clockinput,它的狀態改變由資料輸入決定。
latch是一種在非同步序向邏輯電路系統中用來儲存資訊的一種電子電路。
一個latch可以儲存一位元的資訊,latch通常會有多個一起出現。
flip-flop有一個clockinput,它的狀態改變和clock同步。
flip-flop是一種可以儲存一個位元的電路,且是計數器,暫存器及其他時序控制邏輯電路中的一個基本建構方塊,又名雙穩態複振器(bistablemultivibrator)。
在電子學裡,可應用在數字線路上,其線路圖由邏輯閘組合而成,可記載“1”和“0”資料,其結構均由SRlatch衍生而來,而在一個flip-flop裡,所包括的有“0”,“1”,輸入輸出信號與時脈。
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