《EDA技术与VHDL基础》课后习题答案.docx
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《EDA技术与VHDL基础》课后习题答案
《EDA技术与VHDL基础》课后习题答案
LT
3、C
4、B
5、D
6、B
7、A
8、C
三、简答题
2、
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYnand_3inIS
PORT(a,b,c:
INSTD_LOGIC;
y:
OUTSTD_LOGIC);
END;
ARCHITECTUREbhvOFnand_3inIS
BEGIN
y<=NOT(aANDbANDc);
ENDbhv;
5、0000
6、11110111(247)
第四章VHDL基础
一、填空题
1、顺序语句、并行语句
2、跳出本次循环
3、等待、信号发生变化时
4、函数、过程
5、值类属性、函数类属性、信号类属性、数据类型类属性、数据范围类属性
6、程序调试、时序仿真
7、子程序、子程序
二、选择题
1、B
2、A
3、A
4、C
5、B
6、C
7、D
三、判断题
1、√
2、√
3、√
4、√
5、×
6、×
四、简答题
9、修改正确如下所示:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcountIS
PORT(clk:
INBIT;
q:
OUTBIT_VECTOR(7DOWNTO0));
ENDcount;
ARCHITECTUREaOFcountIS
BEGIN
PROCESS(clk)
IFclk'EVENTANDclk='1'THEN
q<=q+1;
ENDPROCESS;
ENDa;
10、修改正确如下所示:
…
SIGNALinvalue:
ININTEGERRANGE0TO15;
SIGNALoutvalue:
OUTSTD_LOGIC;
…
CASEinvalueIS
WHEN0=>outvalue<='1';
WHEN1=>outvalue<='0';
WHENOTHERS=>NULL;
ENDCASE;
…
11、修改正确如下所示:
ARCHITECTUREbhvOFcom1IS
BEGIN
SIGNALa,b,c:
STD_LOGIC;
pro1:
PROCESS(clk)
BEGIN
IFNOT(clk'EVENTANDclk='1')THEN
x<=aXORbORc;
ENDIF;
ENDPROCESS;
END;
12、
(1)PROCESS(…)--本题中两条IF语句均为信号c进行可能赋值,VHDL语言不允许
IFa=bTHEN
c<=d;
ENDIF;
IFa=4THEN
c<=d+1;
ENDIF;
ENDPROCESS;
(2)ARCHITECTUREbehaveOFmuxIS--同时为q进行多次可能赋值,VHDL语言不允许
BEGIN
q<=i0WHENa='0'ANDb='0'ELSE'0';--WHENELSE语句语法错误
q<=i1WHENa='0'ANDb='1'ELSE'0';
q<=i2WHENa='1'ANDb='0'ELSE'0';
q<=i3WHENa='1'ANDb='1'ELSE'0';
ENDbehave;
13、
next1<=1101WHEN(a='0'ANDb='0')ELSE
dWHENa='0'ELSE
cWHENb='1'ELSE
1011;
15、
(1)、STD_LOGIC_UNSIGNED
(2)、GENERIC
(3)、IN
(4)、width-1(7)
(5)、counter_n
(6)、“00000000”
(7)、clk’EVENTANDclk=’1’
(8)、ELSIF
(9)、ENDIF
(10)、q<=count
16、修改正确如下所示:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYCNT10IS
PORT(clk:
INSTD_LOGIC;
q:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCNT10;
ARCHITECTUREbhvOFCNT10IS
SIGNALq1:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(clk)
BEGIN
IFRISING_EDGE(clk)begin–begin修改为THEN
IFq1<9THEN--q1为STD_LOGIC数据类型,而9为整型不可直接比较
q1<=q1+1;--q1为STD_LOGIC数据类型,而1为整型不可直接相加
ELSE
q1<=(OTHERS=>'0');
ENDIF;
ENDIF;
ENDPROCESS;
q<=q1;
ENDbhv;
17、使用IF语句实现
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux21IS
PORT(ain,bin,sel:
INSTD_LOGIC_VECTOR(1DOWNTO0);
cout:
OUTSTD_LOGIC_VECTOR(1DOWNTO0));
END;
ARCHITECTUREbhvOFmux21IS
SIGNALcout_tmp:
STD_LOGIC_VECTOR(1DOWNTO0);
BEGIN
PROCESS(ain,bin,sel)
BEGIN
IF(sel="00")THENcout_tmp<=ainORbin;
ELSIF(sel="01")THENcout_tmp<=ainXORbin;
ELSIF(sel="10")THENcout_tmp<=ainANDbin;
ELSEcout_tmp<=ainNORbin;
ENDIF;
ENDPROCESS;
cout<=cout_tmp;
ENDbhv;
第五章QuartusⅡ集成开发软件初步
一、填空题
1、实体名
2、FPGA、CPLD
3、.vhd
4、输入、综合、适配、仿真、下载
5、RTLViewer、TechnologyMapViewer
6、功能、参数含义、使用方法、硬件描述语言、模块参数设置
7、mif、hex
8、根目录
二、选择题
1、C
2、D
第七章有限状态机设计
一、设计题
1、
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYztjIS
PORT(clk,reset:
INSTD_LOGIC;
in_a:
INSTD_LOGIC_VECTOR(1DOWNTO0);
out_a:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
END;
ARCHITECTUREbhvOFztjIS
TYPEstateIS(s0,s1,s2,s3);--用枚举类型定义状态,简单直观
SIGNALcurrent_state,next_state:
state;--定义存储现态和次态的信号
BEGIN
p1:
PROCESS(clk)--状态更新进程
BEGIN
IFclk'EVENTANDclk='1'THEN
IFreset='1'THENcurrent_state<=s0;
ELSEcurrent_state<=next_state;
ENDIF;
ENDIF;
ENDPROCESS;
p2:
PROCESS(current_state,in_a)--次态产生进程
BEGIN
CASEcurrent_stateIS
WHENs0=>IFin_a/=”00”THENnext_state<=s1;
ELSEnext_state<=s0;
ENDIF;
WHENs1=>IFin_a=/'”01”THENnext_state<=s2;
ELSEnext_state<=s1;
ENDIF;
WHENs2=>IFin_a=”11”THENnext_state<=s0
ELSEnext_state<=s3;
ENDIF;
WHENs3=>IFin_a/='11'THENnext_state<=s0;
ELSEnext_state<=s3;
ENDIF;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
p3:
PROCESS(current_state)
BEGIN
CASEcurrent_stateIS
WHENs0=>out_a<='”0101”;
WHENs1=>out_a<=”1000”;
WHENs2=>out_a<=”1100”;
WHENs3=>out_a<=”1101”;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
END;
2、
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYztjIS
PORT(clk,reset:
INSTD_LOGIC;
ina:
INSTD_LOGIC_VECTOR(2DOWNTO0);
outa:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
END;
ARCHITECTUREbhvOFztjIS
TYPEstateIS(s0,s1,s2,s3);--用枚举类型定义状态,简单直观
SIGNALcurrent_state,next_state:
state;
BEGIN
p1:
PROCESS(clk)--状态更新进程
BEGIN
IFclk'EVENTANDclk='1'THEN
IFreset='1'THENcurrent_state<=s0;
ELSEcurrent_state<=next_state;
ENDIF;
ENDIF;
ENDPROCESS;
p2:
PROCESS(current_state,ina)
BEGIN
CASEcurrent_stateIS
WHENs0=>IFina=”101”THENouta<=”0010”;
ELSIFina=”111”THENouta<=”1100”;
ENDIF;
IFina=”000”THENnext_state<=s1;
ELSEnext_state<=s0;
ENDIF;
WHENs1=>outa<=”1001”;
IFina=”110”THENnext_state<=s2;
ELSEnext_state<=s1;
ENDIF;
WHENs2=>outa<=”1111”;
IFina=”011”THENnext_state<=s1;
ELSIFina=”100”THENnext_state<=s2;
ELSEnext_state<=s3;
ENDIF;
WHENs3=>IFina=”101”THENouta<=”1101”;
ELSIFina=”011”THENouta<=”1100”;
ENDIF;
IFina=”010”THENnext_state<=s0;
ELSEnext_state<=s1;
ENDIF;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
END;
3、
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYztjIS
PORT(clk,reset:
INSTD_LOGIC;
ina:
INSTD_LOGIC_VECTOR(1DOWNTO0);
outa:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
END;
ARCHITECTUREbhvOFztjIS
TYPEstateIS(s0,s1,s2,s3);--用枚举类型定义状态,简单直观
SIGNALstate:
istate;
BEGIN
p1:
PROCESS(clk)
BEGIN
IFclk'EVENTANDclk='1'THEN
IFreset='1'THENstate<=s0;result<='0';
ELSE
CASEstateIS
WHENs0=>outa<=”0000”;
IFina=”00”THENstate<=s1;
ELSEstate<=s0;
ENDIF;
WHENs1=>outa<=”0001”;
IFina=”01”THENstate<=s2;
ELSEstate<=s1;
ENDIF;
WHENs2=>outa<=”1100”;
IFina=”11”THENstate<=s3;
ELSEstate<=s0;
ENDIF;
WHENs3=>outa<=”1111”;
IFina=”00”THENstate<=s0;
ELSEstate<=s3;
ENDIF;
WHENOTHERS=>NULL;
ENDCASE;
ENDIF;
ENDIF;
ENDPROCESS;
END;
第九章VHDL基本逻辑电路设计
一、填空题
1、输入信号、所处状态
2、组合逻辑、时序逻辑
3、触发器、1
4、D触发器、RS触发器、JK触发器、T触发器
二、选择题
1、A
2、C