pcf8591英文毕设.docx

pcf8591英文毕设.docx

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pcf8591英文毕设

8-bitA/DandD/AconverterPCF8591

1.FEATURES

.Singlepowersupply

.Operatingsupplyvoltage2.5Vto

6.0V

.Lowstandbycurrent

.Serialinput/outputviaI2C-bus

.Addressby3hardwareaddresspins

.SamplingrategivenbyI2C-busspeed

.4analoginputsprogrammableassingle-endedordifferentinputs

.Auto-incrementedchannelselection

.AnalogvoltagerangefromVSStoVDD

.On-chiptrackandholdcircuit

.8-bitsuccessiveapproximationA/Dconversion

.MultiplyingDACwithoneanalogoutput

2.APPLICATION

.Closedloopcontrolsystems

.Lowpowerconverterforremotedataacquisition

3.GENERALDESCRIPTION

ThePCF8591isasingle-chip,single-supplylowpower8-bitCOMSdataacquisitiondevicewithfouranaloginputs,oneanalogoutput,andaserialI2C-businterface.

ThreeaddresspinsAD,A1andA2areusedforprogrammingthehardwareaddress,allowingtheuseupto8devicesconnectedtotheI2C-buswithoutadditionalhardware.

Address,controlanddatatoandfromthedevicearetransferredseriallyviathetwo-linebidirectionalI2C-bus.

ThefunctionsofthedevicesincludeinputMultiplexing,on-chiptrackandholdfunction,

8-bitanalog-to-digitalconversionandan8-bitdigital-to-analogconversion.themaximumconversionrareisgivenbythemaximumspeedoftheI2C-bus.

4.ORDERINGINFORMATION

TYPENUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

PCF8591P

DIP16

Plasticdualin-linepackage,16leads

SOT38-4

PCF8591T

SO16

Plasticsmalloutlinepackage,16leads

SOT162-1

7.FUNCTIONDESCRIPTION

7.1EachPCF8591deviceinanI2C-bussystemisactivatedbysendingavalidaddresstothedevice.Theaddressconsistsofafixedpartandaprogrammablepart.TheprogrammablepartmustbesentaccordingtotheaddresspinsA0,A1andA2.TheaddressalwayshastobesentasthefirstbyteafterthestartconditionintheI2C-busprotocol.Thelastbitoftheaddressbyteistheread/write-bitwhichsetsthedirectionofthefollowingdatatransfer.

7.2CONTROLBYTE

ThesecondbytesenttoaPCF8591devicewillbestoredinitscontrolregisterandisrequiredtocontrolthedevicefunction.Theuppernibbleofthecontrolregisterisusedforenablingtheanalogoutput,andforprogrammingtheanaloginputsassingle-endedordifferentialinputs.Thelowernibbleselectiononeoftheanaloginputchannelsdefinedbytheuppernibble.Iftheauto-incrementflagisset,thechannelnumberisincrementedautomaticallyaftereachA/Dconversion.

Iftheauto-incrementmodeisdesiredinapplicationswheretheinternaloscillatortoruncontinuously,therebypreventingconversionerrorsresultingfromoscillatorstart-updelay.Theanalogoutputenableflagmayberesetatothertimestoreducequiescentpowerconsumption.

Theselectionofanon-exitinginputchannelresultsinthehighestavailablechannelnumberbeingallocated.Therefore,iftheauto-incrementflagisset,thenextselectedchannelwillbealwayschannel0.Afterapower-onresetconditionallbitsofthecontrolregisterareresettologic0.TheD/Aconverterandtheoscillatoraredisabledforpowersaving.Theanalogoutputisswitchedtoahigh-impedancestate（seeFig.5）.

Fig.5Controlbyte

7.3D/Aconversion

ThethirdbytesenttoaPCF8591deviceisstoredintheDACdataregisterandisconvertedtothecorrespondinganalogvoltageusingtheon-chipD/Aconverter.Thisconverterconsistsofaresistordividerchainconnectedtotheexternalreferencevoltagewith256tapsandselectionswitches.Thetap-decoderswitchesoneofthesetapstotheDACoutputline.（seeFig.6）

7.4A/Dconversion

TheA/Dconvertermakesuseofthesuccessiveapproximationconversiontechnique.Theon-chipD/Aconverterandahigh-gaincomparatorareusedtemporarilyduringanA/Dconversioncycle.

AnA/DconversioncycleisalwaysstartedaftersendingavalidreadmodeaddresstoaPCF8591device.TheA/Dconversioncycleistriggeredatthetrailingedgeoftheacknowledgeclockpulseandisexecutedwhiletransmittingtheresultofthepreviousconversion（seeFig.7）.

Onceaconversioncycleistriggeredaninputvoltagesampleoftheselectedchannelisstoredonthechipandisconvertedtothecorresponding8-bitbinarycode.Samplespickedupfromdifferentialareconvertedtoan8-bittwoscomplementcode.（seeFig.8Fig.9）.

TheconversionresultisstoredintheADCdataregisterandawaitstransmission.Iftheauto-incrementflagissetthenextchannelisselected.

Thefirstbytetransmittedinareadcyclecontainstheconversionresultcodeofthepreviousreadcycle.Afterapower-onresetconditionthefirstbytereadisahexadecimal80.TheprotocolofanI2C-busreadcycleisshowninchapter8.

ThemaximumA/DconversionrateisgivenbyactualspeedoftheI2C-bus.

A/Dconversionsequence

7.5Referencevoltage

FortheA/DandD/Aconversioneitherastableexternalvoltagereferenceorthesupplyvoltagehastobeappliedtotheresistordividerchain（pinsVREFandAGND）.

TheAGNDpinhastobeconnectedtothesystemanaloggroundandmayhaveaDCoff-setwithreferencetoVSSAlowfrequencymaybeappliedtotheVREFandAGNDpins.ThisallowstheuseofD/Aconverterasaone-quadrantmultiplier.

TheA/Dconvertermayalsobeusedoneortwoquadrantanalogdivider.Theanaloginputvoltageisdividedbythereferencevoltage.Theresultisconvertedtoabinarycode.Inthisapplicationtheuserhastokeepthereferencevoltagestableduringtheconversioncycle.

7.6Oscillator

Anon-shiposcillatorgeneratestheclocksignalrequiredfortheA/Dconversioncycleandforrefreshingtheauto-zeroedbufferamplifier.WhenusingthisoscillatortheEXTpinhastobeconnectedtoVSS.AttheOSCpintheoscillatorfrequencyisavailable.

IftheEXTpinisconnectedtoVDDtheoscillatoroutputOSCisswitchedtoahigh-impedancestateallowingtheusertofeedanexternalclocksignaltoOSC.

8.CHARACTERISTICSOFTHEI2C-BUS

TheI2C-busisforbidirectional,two-linecommunicationbetweendifferentICsormodules.Thetwolinesareaserialdataline（SDA）andaserialclockline（SCL）.Bothlinesmustbeconnectedtoapositivesupplyviaapull-upresister.Datatransfermaybeinitiatedonlywhenthebusisnotbusy.

8.1Bittransfer

Onedatabitistransferredduringeachclockpulse.ThedataontheSDAlinemustremainstableduringtheHIGHperiodoftheclockpulseaschangesinthedatalineatthistimewillbeinterpretedasacontrolsignal.

Bittransfer

8.2Startandstopconditions

BothdataandclocklinesremainHIGHwhenthebusisnotbusy.AHIGH-to-LOWtransitionofthedataline,whiletheclockisHIGH,isdefinedasthestartcondition（S）.ALOW-to-HIGHtransitionofthedatalinewhiletheclockisHIGH,isdefinedasthestopcondition（P）.

DefinitionofSTARTandSTOPcondition

8.3Systemconfiguration

Adevicegeneratingamessageisa‘transmitter’,adevicereceivingamessageisthe‘receiver’.Thedevicethatcontrolsthemessageisthe‘mater’andthedeviceswhicharecontrolledbythemasterarethe‘slave’.

Systemconfiguration

8.4Acknowledge

Thenumberofdatabytestransferredbetweenthestartandstopconditionsfromtransmittertoreceiverisnotlimited.Eachdatabyteofeightbitsisfollowedbyoneacknowledgebit.TheacknowledgebitisaHIGHlevelputonthebusbythetransmitterwhereasthemasteralsogeneratesanextraacknowledgerelatedclockpulse.Aslavereceiverwhichisaddressedmustgenerateanacknowledgeafterthereceptionofeachbyte.Alsoamastermustgenerateanacknowledgeafterthereceptionofeachbytethathasbeenclockedoutoftheslavetransmitter.ThedevicethatacknowledgeshastopulldowntheSDAlineduringtheacknowledgeclockpulse,sothattheSDAlineisstableLOWduringtheHIGHperiodoftheacknowledgerelatedclockpulse.Amasterreceivermustsignalanendofdatatothetransmitterbynotgeneratinganacknowledgeonthelastbytethathasbeenclockedoutoftheslave.InthiseventthetransmittermustleavethedatalineHIGHtoenablethemastertogenerateastopcondition.

AcknowledgementontheI2C-bus

8.5I2C-busprotocol

AfterastartconditionavalidhardwareaddresshastobesenttoaPCF8591device.Theread/writebitdefinesthedirectionofthefollowingsingleormultiplebytedatatransfer.Fortheformatandthetimingofthestartcondition（S）,thestopcondition（p）andtheacknowledgebit（A）refertotheI2C-buscharacteristics.Inthewritemodeadatatransferisterminatedbysendingeitherastopconditionorthestartconditionofthenextdatatransfer.

Busprotocolforwritemode,D/Aconversion

Busprotocolforreadmode,A/Dconversion