基于VHDL语言的数字钟设计.docx
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基于VHDL语言的数字钟设计
一．程序代码及其仿真：
1．cnt60子模块代码：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
ENTITYV_cnt60IS
PORT（clk:
INstd_logic;
Q0,Q1,Q2,Q3,Q4,Q5,Q6,QC:
OUTstd_logic）;
ENDV_cnt60;
ARCHITECTUREfuncOFV_cnt60IS
SIGNALcount1:
std_logic_vector（3downto0）;
SIGNALcount2:
std_logic_vector（3downto0）;
SIGNALcarryin:
std_logic;
BEGIN
Q0<=count1（0）;
Q1<=count1
（1）;
Q2<=count1
（2）;
Q3<=count1（3）;
Q4<=count2（0）;
Q5<=count2
（1）;
Q6<=count2
（2）;
QC<=carryin;
process（clk）
BEGIN
if（clk'eventANDclk='1'）then
carryin<='0';
if（count1="1001"）then
count1<="0000";
count2<=count2+1;
else
count1<=count1+1;
ENDif;
if（count2="0101"ANDcount1="1001"）then
count2<="0000";
count1<="0000";
carryin<='1';
ENDif;
ENDif;
ENDprocess;
ENDfunc;
cnt60仿真波形：
2．cnt24子模块代码：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
ENTITYV_cnt24IS
PORT（clk:
INstd_logic;
Q0,Q1,Q2,Q3,Q4,Q5:
OUTstd_logic）;
ENDV_cnt24;
ARCHITECTUREfunc_cnt24OFV_cnt24IS
SIGNALcount1:
std_logic_vector（3downto0）;
SIGNALcount2:
std_logic_vector（3downto0）;
SIGNALcarryin:
std_logic;
BEGIN
Q0<=count1（0）;
Q1<=count1
（1）;
Q2<=count1
（2）;
Q3<=count1（3）;
Q4<=count2（0）;
Q5<=count2
（1）;
process（clk）
BEGIN
if（clk'eventandclk='1'）then
if（count1="1001"）then
count1<="0000";
count2<=count2+1;
else
count1<=count1+1;
ENDif;
if（count2="0010"ANDcount1="0011"）then
count2<="0000";
count1<="0000";
ENDif;
ENDif;
ENDprocess;
ENDfunc_cnt24;
cnt24仿真波形：
3．cnt1000字模块代码：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityV_cnt1000is
port（clk:
instd_logic;
cnt1000:
outstd_logic;
clk_c:
outstd_logic）;
endV_cnt1000;
architecturebhvofV_cnt1000is
signaltmp:
std_logic_vector（9downto0）;
signalamp:
std_logic_vector（8downto0）;
begin
process（clk）
begin
if（clk'eventandclk='1'）then
if（tmp=1023）thentmp<="0000000000";
elsetmp<=tmp+1;
endif;
if（tmp<511）thencnt1000<='0';
elsecnt1000<='1';
endif;
endif;
endprocess;
process（clk）
begin
if（clk'eventandclk='1'）then
if（amp=511）thenamp<="000000000";
elseamp<=amp+1;
endif;
if（amp<255）thenclk_c<='0';
elseclk_c<='1';
endif;
endif;
endprocess;
endbhv;
cnt1000仿真波形：
4．clk_c子模块代码：
libraryIEEE;
useIEEE.std_logic_1164.all;
useIEEE.std_logic_unsigned.all;
ENTITYV_clk_cIS
PORT
（clk,CLK_C,M1,S1,SS,MM,HH,CTRL:
INSTD_LOGIC;
CLKS,CLKM,CLKH:
OUTSTD_LOGIC）;
ENDV_clk_c;
ARCHITECTUREfuncOFV_clk_cIS
BEGIN
process
begin
CLKS<=（CTRLANDCLK）OR（（NOTCTRL）ANDHHANDMMAND（NOTSS）ANDCLK_C）;
CLKM<=（CTRLANDS1）OR（（NOTCTRL）ANDHHAND（NOTMM）ANDSSANDCLK_C）;
CLKH<=（CTRLANDM1）OR（（NOTCTRL）AND（NOTHH）ANDMMANDSSANDCLK_C）;
ENDprocess;
ENDfunc;
5．display子模块代码：
libraryIEEE;
useIEEE.std_logic_1164.all;
useIEEE.std_logic_unsigned.all;
ENTITYdisplayIS
PORT
（clk:
INstd_logic;
LED1Q_0,LED1Q_1,LED1Q_2,LED1Q_3:
INstd_logic;
LED2Q_0,LED2Q_1,LED2Q_2,LED2Q_3:
INstd_logic;
LED3Q_0,LED3Q_1,LED3Q_2,LED3Q_3:
INstd_logic;
LED4Q_0,LED4Q_1,LED4Q_2,LED4Q_3:
INstd_logic;
LED5Q_0,LED5Q_1,LED5Q_2,LED5Q_3:
INstd_logic;
LED6Q_0,LED6Q_1,LED6Q_2,LED6Q_3:
INstd_logic;
LED1,LED2,LED3,LED4,LED5,LED6:
OUTstd_logic;
SE_A,SE_B,SE_C,SE_D,SE_E,SE_F,SE_G:
OUTstd_logic）;
ENDdisplay;
ARCHITECTUREfuncOFdisplayIS
SIGNALctrl:
std_logic_vector（2downto0）;
SIGNALcode:
std_logic_vector（3downto0）;
BEGIN
process（ctrl）
BEGIN
CASEctrlIS
WHEN"000"=>LED1<='1';
LED2<='0';
LED3<='0';
LED4<='0';
LED5<='0';
LED6<='0';
code（0）<=LED1Q_0;
code
（1）<=LED1Q_1;
code
（2）<=LED1Q_2;
code（3）<=LED1Q_3;
WHEN"001"=>LED1<='0';
LED2<='1';
LED3<='0';
LED4<='0';
LED5<='0';
LED6<='0';
code（0）<=LED2Q_0;
code
（1）<=LED2Q_1;
code
（2）<=LED2Q_2;
code（3）<=LED2Q_3;
WHEN"010"=>LED1<='0';
LED2<='0';
LED3<='1';
LED4<='0';
LED5<='0';
LED6<='0';code（0）<=LED3Q_0;
code
（1）<=LED3Q_1;
code
（2）<=LED3Q_2;
code（3）<=LED3Q_3;
WHEN"011"=>LED1<='0';
LED2<='0';
LED3<='0';
LED4<='1';
LED5<='0';
LED6<='0';code（0）<=LED4Q_0;
code
（1）<=LED4Q_1;
code
（2）<=LED4Q_2;
code（3）<=LED4Q_3;
WHEN"100"=>LED1<='0';
LED2<='0';
LED3<='0';
LED4<='0';
LED5<='1';
LED6<='0';
code（0）<=LED5Q_0;
code
（1）<=LED5Q_1;
code
（2）<=LED5Q_2;
code（3）<=LED5Q_3;
WHEN"101"=>LED1<='0';
LED2<='0';
LED3<='0';
LED4<='0';
LED5<='0';
LED6<='1';code（0）<=LED6Q_0;
code
（1）<=LED6Q_1;
code
（2）<=LED6Q_2;
code（3）<=LED6Q_3;
WHENOTHERS=>NULL;
ENDCASE;
ENDprocess;
process（code）
BEGIN
CASEcodeIS
WHEN"0000"=>
SE_A<='1';SE_B<='1';SE_C<='1';SE_D<='1';SE_E<='1';SE_F<='1';SE_G<='0';
WHEN"0001"=>
SE_A<='0';SE_B<='1';SE_C<='1';SE_D<='0';SE_E<='0';SE_F<='0';SE_G<='0';
WHEN"0010"=>
SE_A<='1';SE_B<='1';SE_C<='0';SE_D<='1';SE_E<='1';SE_F<='0';SE_G<='1';
WHEN"0011"=>
SE_A<='1';SE_B<='1';SE_C<='1';SE_D<='1';SE_E<='0';SE_F<='0';SE_G<='1';
WHEN"0100"=>
SE_A<='0';SE_B<='1';SE_C<='1';SE_D<='0';SE_E<='0';SE_F<='1';SE_G<='1';
WHEN"0101"=>
SE_A<='1';SE_B<='0';SE_C<='1';SE_D<='1';SE_E<='0';SE_F<='1';SE_G<='1';
WHEN"0110"=>
SE_A<='1';SE_B<='0';SE_C<='1';SE_D<='1';SE_E<='1';SE_F<='1';SE_G<='1';
WHEN"0111"=>
SE_A<='1';SE_B<='1';SE_C<='1';SE_D<='0';SE_E<='0';SE_F<='0';SE_G<='0';
WHEN"1000"=>
SE_A<='1';SE_B<='1';SE_C<='1';SE_D<='1';SE_E<='1';SE_F<='1';SE_G<='1';
WHEN"1001"=>
SE_A<='1';SE_B<='1';SE_C<='1';SE_D<='1';SE_E<='0';SE_F<='1';SE_G<='1';
WHEN"1010"=>
SE_A<='1';SE_B<='1';SE_C<='1';SE_D<='0';SE_E<='1';SE_F<='1';SE_G<='1';
WHEN"1011"=>
SE_A<='0';SE_B<='0';SE_C<='1';SE_D<='1';SE_E<='1';SE_F<='1';SE_G<='1';
WHEN"1100"=>
SE_A<='1';SE_B<='0';SE_C<='0';SE_D<='1';SE_E<='1';SE_F<='1';SE_G<='0';
WHEN"1101"=>
SE_A<='0';SE_B<='1';SE_C<='1';SE_D<='1';SE_E<='1';SE_F<='0';SE_G<='1';
WHEN"1110"=>
SE_A<='1';SE_B<='0';SE_C<='0';SE_D<='1';SE_E<='1';SE_F<='1';SE_G<='1';
WHEN"1111"=>
SE_A<='1';SE_B<='0';SE_C<='0';SE_D<='0';SE_E<='1';SE_F<='1';SE_G<='1';
WHENOTHERS=>
SE_A<='0';SE_B<='0';SE_C<='0';SE_D<='0';SE_E<='0';SE_F<='0';SE_G<='0';
ENDCASE;
ENDprocess;
process（clk）
BEGIN
if（clk'eventandclk='1'）then
ctrl<=ctrl+1;
if（ctrl="101"）then
ctrl<="000";
ENDif;
ENDif;
ENDprocess;
ENDfunc;
display仿真波形：
6．de4_7子模块代码：
libraryieee;
useieee.STD_logic_1164.ALL;
useieee.STD_logic_unsigned.ALL;
ENTITYV_de4_7IS
PORT（a,b,c,d:
instd_logic;
se_a,se_b,se_c,se_d,se_e,se_f,se_g:
outstd_logic）;
ENDV_de4_7;
ARCHITECTUREactde4_7OFV_de4_7IS
signalsegment:
std_logic_vector（6downto0）;
signalinput:
std_logic_vector（3downto0）;
begin
se_a<=segment（0）;
se_b<=segment
（1）;
se_c<=segment
（2）;
se_d<=segment（3）;
se_e<=segment（4）;
se_f<=segment（5）;
se_g<=segment（6）;
input（0）<=d;
input
（1）<=c;
input
（2）<=b;
input（3）<=a;
process（a,b,c,d）
begin
caseinputis
when"0000"=>segment<="1111110";
when"0001"=>segment<="0110000";
when"0010"=>segment<="1101101";
when"0011"=>segment<="1111001";
when"0100"=>segment<="0110011";
when"0101"=>segment<="1011011";
when"0110"=>segment<="1011111";
when"0111"=>segment<="1110000";
when"1000"=>segment<="1111111";
when"1001"=>segment<="1111011";
when"1010"=>segment<="1110111";
when"1011"=>segment<="0011111";
when"1100"=>segment<="1001110";
when"1101"=>segment<="0111101";
when"1110"=>segment<="1001111";
when"1111"=>segment<="1000111";
whenothers=>segment<="0000000";
endcase;
endprocess;
endactde4_7;
de4_7仿真波形：
7.mul8_1子模块代码：
LIBRARYIEEE;
useieee.STD_LOGIC_1164.ALL;
ENTITYV_mul8_1IS
PORT（ST:
INSTD_LOGIC;
A:
INSTD_LOGIC_VECTOR（2DOWNTO0）;
D:
INSTD_LOGIC_VECTOR（7DOWNTO0）;
Q:
OUTSTD_LOGIC）;
ENDV_mul8_1;
ARCHITECTUREHBVOFV_mul8_1IS
SIGNALQ1:
STD_LOGIC;
BEGIN
PROCESS（a）
BEGIN
IFST='1'THENQ1<='0';
ELSE
CASEaIS
WHEN"000"=>Q1<=D（0）;
WHEN"001"=>Q1<=D
（1）;
WHEN"010"=>Q1<=D
（2）;
WHEN"011"=>Q1<=D（3）;
WHEN"100"=>Q1<=D（4）;
WHEN"101"=>Q1<=D（5）;
WHEN"110"=>Q1<=D（6）;
WHEN"111"=>Q1<=D（7）;
WHENOTHERS=>NULL;
ENDCASE;
ENDIF;
ENDPROCESS;
Q<=Q1;
ENDHBV;
mul8_1仿真波形：
二．总体资源占用率：
50%
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