福建工程学院电子产品设计程序.docx
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福建工程学院电子产品设计程序
adder8
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_unsigned.all;
ENTITYadder8IS
PORT
（
A,B:
INSTD_LOGIC_VECTOR（7DOWNTO0）;
Ci_1:
INSTD_LOGIC;
S:
OUTSTD_LOGIC_VECTOR（7DOWNTO0）;
Ci:
OUTSTD_LOGIC
）;
ENDENTITYadder8;
ARCHITECTUREaOFadder8IS
COMPONENTFADDERIS
PORT
（
Ai,Bi,Ci_1:
INSTD_LOGIC;
Si,Ci:
OUTSTD_LOGIC
）;
ENDCOMPONENT;
SIGNALE:
STD_LOGIC_VECTOR（6DOWNTO0）;
BEGIN
U1:
FADDERPORTMAP（Ai=>A（0）,Bi=>B（0）,Ci_1=>Ci_1,Si=>S（0）,Ci=>E（0））;
U2:
FADDERPORTMAP（Ai=>A
（1）,Bi=>B
（1）,Ci_1=>E（0）,Si=>S
（1）,Ci=>E
（1））;
U3:
FADDERPORTMAP（Ai=>A
（2）,Bi=>B
（2）,Ci_1=>E
（1）,Si=>S
（2）,Ci=>E
（2））;
U4:
FADDERPORTMAP（Ai=>A（3）,Bi=>B（3）,Ci_1=>E
（2）,Si=>S（3）,Ci=>E（3））;
U5:
FADDERPORTMAP（Ai=>A（4）,Bi=>B（4）,Ci_1=>E（3）,Si=>S（4）,Ci=>E（4））;
U6:
FADDERPORTMAP（Ai=>A（5）,Bi=>B（5）,Ci_1=>E（4）,Si=>S（5）,Ci=>E（5））;
U7:
FADDERPORTMAP（Ai=>A（6）,Bi=>B（6）,Ci_1=>E（5）,Si=>S（6）,Ci=>E（6））;
U8:
FADDERPORTMAP（Ai=>A（7）,Bi=>B（7）,Ci_1=>E（6）,Si=>S（7）,Ci=>Ci）;
ENDARCHITECTUREa;
adder8a
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_unsigned.all;
ENTITYadder8aIS
PORT
（
A,B:
INSTD_LOGIC_VECTOR（7DOWNTO0）;
Ci_1:
INSTD_LOGIC;
S:
OUTSTD_LOGIC_VECTOR（7DOWNTO0）;
Ci:
OUTSTD_LOGIC
）;
ENDENTITYadder8a;
ARCHITECTUREaOFadder8aIS
signalsum:
std_logic_vector（8downto0）;
begin
sum<=（'0'&A）+（'0'&B）+Ci_1;
S<=SUM（7DOWNTO0）;
Ci<=SUM（8）;
ENDA;
adder8b
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYADDER8BIS
PORT（CIN:
INSTD_LOGIC;
A,B:
INSTD_LOGIC_VECTOR（7DOWNTO0）;
S:
OUTSTD_LOGIC_VECTOR（8DOWNTO0））;
ENDADDER8B;
ARCHITECTUREAOFADDER8BIS
SIGNALSINT,AA,BB:
STD_LOGIC_VECTOR（8DOWNTO0）;
BEGIN
AA<='0'&A;
BB<='0'&B;
SINT<=AA+BB+CIN;
S<=SINT;
ENDA;
andarith
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYANDARITHIS
PORT（ABIN:
INSTD_LOGIC;
DIN:
INSTD_LOGIC_VECTOR（7DOWNTO0）;
DOUT:
OUTSTD_LOGIC_VECTOR（7DOWNTO0））;
ENDANDARITH;
ARCHITECTUREAOFANDARITHIS
BEGIN
PROCESS（ABIN,DIN）
BEGIN
--FORIIN0TO7LOOP
--DOUT（I）<=DIN（I）ANDABIN;
--ENDLOOP;
IFABIN='1'THENDOUT<=DIN;
ELSEDOUT<="00000000";
ENDIF;
ENDPROCESS;
ENDA;
arictl
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYARICTLIS
PORT（CLK,START:
INSTD_LOGIC;
CLKOUT:
BUFFERSTD_LOGIC;
RSTALL:
OUTSTD_LOGIC）;
ENDARICTL;
ARCHITECTUREAOFARICTLIS
SIGNALCNT:
INTEGERRANGE0TO16;
BEGIN
PROCESS（CLK,START）
BEGIN
RSTALL<=START;
IFSTART='1'THENCNT<=0;CLKOUT<='0';
ELSIFCLK'EVENTANDCLK='1'THEN
IFCNT<16THENCNT<=CNT+1;CLKOUT<=NOTCLKOUT;
ELSECLKOUT<='0';
ENDIF;
ENDIF;
ENDPROCESS;
ENDA;
cnt4
libraryieee;
useieee.std_logic_1164.all;
entitycnt4is
port（clk:
inbit;
q:
bufferintegerrange15downto0）;
endcnt4;
architectureaofcnt4is
begin
process（clk）
begin
ifclk'eventandclk='1'thenq<=q-1;
endif;
endprocess;
enda;
cnt10
LIBRARYieee;
USEieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
ENTITYcnt10IS
PORT
（
data:
INstd_logic_vector（3downto0）;
clk:
INSTD_LOGIC;
rst:
INSTD_LOGIC;
en:
INSTD_LOGIC;
load:
INSTD_LOGIC;
as:
INSTD_LOGIC;
dout:
OUTstd_logic_vector（3downto0）;
cout:
outstd_logic
）;
ENDcnt10;
ARCHITECTUREaOFcnt10IS
SIGNALcnt:
std_logic_vector（3downto0）;
BEGIN
PROCESS（clk,rst,en,load）
BEGIN
IFrst='0'THENcnt<="0000";
ELSIF（clk'EVENTANDclk='1'）THEN
IFload='0'THENcnt<=data;
ELSIFen='1'THEN
IFAS='0'THEN
ifcnt<9thencnt<=cnt+1;cout<='0';
elsecnt<="0000";cout<='1';
ENDIF;
ELSE
ifcnt>0thencnt<=cnt-1;cout<='0';
elsecnt<="1001";cout<='1';
ENDIF;
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
dout<=cnt;
ENDa;
cnt10a
LIBRARYieee;
USEieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
ENTITYcnt10aIS
PORT
（clk,rst,en,load:
INSTD_LOGIC;
data:
INstd_logic_vector（3downto0）;
dout:
OUTstd_logic_vector（3downto0）;
cout:
outstd_logic
）;
ENDcnt10a;
ARCHITECTUREaOFcnt10aIS
SIGNALq:
std_logic_vector（3downto0）;
BEGIN
PROCESS（clk,rst,en,load）
BEGIN
IFrst='0'THENq<="0000";
ELSIF（clk'EVENTANDclk='1'）THEN
IFload='0'THENq<=data;
ELSIFen='1'THEN
IFq<9thenq<=q+1;cout<='0';
elseq<="0000";cout<='1';
ENDIF;
ENDIF;
ENDIF;
--ifq="1001"thencout<='1';
--elsecout<='0';
--endif;
ENDPROCESS;
dout<=q;
ENDa;
cnt100tb
LIBRARYieee;
USEieee.std_logic_1164.all;
LIBRARYwork;
ENTITYcnt100tbIS
port
（
clk:
INSTD_LOGIC;
rst:
INSTD_LOGIC;
en:
INSTD_LOGIC;
load:
INSTD_LOGIC;
as:
INSTD_LOGIC;
data1:
INSTD_LOGIC_VECTOR（3downto0）;
data2:
INSTD_LOGIC_VECTOR（3downto0）;
cout:
OUTSTD_LOGIC;
cout0:
OUTSTD_LOGIC;
dout1:
OUTSTD_LOGIC_VECTOR（3downto0）;
dout2:
OUTSTD_LOGIC_VECTOR（3downto0）
）;
ENDcnt100tb;
ARCHITECTUREbdf_typeOFcnt100tbIS
componentcnt10
PORT（clk:
INSTD_LOGIC;
rst:
INSTD_LOGIC;
en:
INSTD_LOGIC;
load:
INSTD_LOGIC;
as:
INSTD_LOGIC;
data:
INSTD_LOGIC_VECTOR（3downto0）;
cout:
OUTSTD_LOGIC;
dout:
OUTSTD_LOGIC_VECTOR（3downto0）
）;
endcomponent;
signalcout0_ALTERA_SYNTHESIZED:
STD_LOGIC;
signalcout_ALTERA_SYNTHESIZED:
STD_LOGIC_VECTOR（1to1）;
signaldout1_ALTERA_SYNTHESIZED:
STD_LOGIC_VECTOR（3downto0）;
signalSYNTHESIZED_WIRE_0:
STD_LOGIC;
BEGIN
b2v_inst:
cnt10
PORTMAP（clk=>clk,
rst=>rst,
en=>en,
load=>load,
as=>as,
data=>data1,
cout=>cout0_ALTERA_SYNTHESIZED,
dout=>dout1_ALTERA_SYNTHESIZED）;
b2v_inst1:
cnt10
PORTMAP（clk=>clk,
rst=>rst,
en=>SYNTHESIZED_WIRE_0,
load=>load,
as=>as,
data=>data2,
cout=>cout_ALTERA_SYNTHESIZED,
dout=>dout2）;
SYNTHESIZED_WIRE_0<=dout1_ALTERA_SYNTHESIZED（0）ANDdout1_ALTERA_SYNTHESIZED（3）;
cout<=cout0_ALTERA_SYNTHESIZEDANDcout_ALTERA_SYNTHESIZED;
cout0<=cout0_ALTERA_SYNTHESIZED;
dout1<=dout1_ALTERA_SYNTHESIZED;
END;
d
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYDIS
PORT（CLK:
INSTD_LOGIC;
D:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC
）;
ENDD;
ARCHITECTUREAOFDIS
SIGNALQ1:
STD_LOGIC;
BEGIN
PROCESS（CLK）
BEGIN
IFCLK'EVENTANDCLK='1'THENQ1<=D;
ENDIF;
Q<=Q1;
ENDPROCESS;
ENDA;
d-srg
LIBRARYieee;
USEieee.std_logic_1164.all;
LIBRARYwork;
ENTITYd_srgIS
PORT
（
clk:
INSTD_LOGIC;
d:
INSTD_LOGIC;
q:
OUTSTD_LOGIC_VECTOR（7DOWNTO0）
）;
ENDd_srg;
ARCHITECTUREbdf_typeOFd_srgIS
COMPONENTmydff
PORT（CLK:
INSTD_LOGIC;
D:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC
）;
ENDCOMPONENT;
SIGNALq_ALTERA_SYNTHESIZED:
STD_LOGIC_VECTOR（7DOWNTO0）;
BEGIN
b2v_inst:
mydff
PORTMAP（CLK=>clk,
D=>d,
Q=>q_ALTERA_SYNTHESIZED（0））;
b2v_inst1:
mydff
PORTMAP（CLK=>clk,
D=>q_ALTERA_SYNTHESIZED（0）,
Q=>q_ALTERA_SYNTHESIZED
（1））;
b2v_inst2:
mydff
PORTMAP（CLK=>clk,
D=>q_ALTERA_SYNTHESIZED
（1）,
Q=>q_ALTERA_SYNTHESIZED
（2））;
b2v_inst3:
mydff
PORTMAP（CLK=>clk,
D=>q_ALTERA_SYNTHESIZED
（2）,
Q=>q_ALTERA_SYNTHESIZED（3））;
b2v_inst4:
mydff
PORTMAP（CLK=>clk,
D=>q_ALTERA_SYNTHESIZED（3）,
Q=>q_ALTERA_SYNTHESIZED（4））;
b2v_inst5:
mydff
PORTMAP（CLK=>clk,
D=>q_ALTERA_SYNTHESIZED（4）,
Q=>q_ALTERA_SYNTHESIZED（5））;
b2v_inst6:
mydff
PORTMAP（CLK=>clk,
D=>q_ALTERA_SYNTHESIZED（5）,
Q=>q_ALTERA_SYNTHESIZED（6））;
b2v_inst7:
mydff
PORTMAP（CLK=>clk,
D=>q_ALTERA_SYNTHESIZED（6）,
Q=>q_ALTERA_SYNTHESIZED（7））;
q<=q_ALTERA_SYNTHESIZED;
ENDbdf_type;
d2
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYD2IS
PORT（CLK:
INSTD_LOGIC;
D:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC
）;
ENDD2;
ARCHITECTUREAOFD2IS
--SIGNALQ1:
STD_LOGIC;
BEGIN
PROCESS（CLK）
BEGIN
IFCLK'EVENTANDCLK='1'THENQ<=D;
ENDIF;
--Q<=Q1;
ENDPROCESS;
ENDA;
decode2-4
libraryieee;
useieee.std_logic_1164.all;
entitydecode2_4is
port（a:
instd_logic_vector（1downto0）;
b:
outstd_logic_vector（3downto0））;
enddecode2_4;
architectureaofdecode2_4is
begin
process（a）
begin
caseais
when"00"=>b<="1110";
when"01"=>b<="1101";
when"10"=>b<="1011";
when"11"=>b<="0111";
whenothers=>b<="0000";
endcase;
endprocess;
enda;
decode7
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYDECODE7IS
PORT（
NUM:
INSTD_LOGIC_VECTOR（3DOWNTO0）;
LOUT:
OUTSTD_LOGIC_VECTOR（6DOWNTO0））;
ENDDECODE7;
ARCHITECTUREaOFDECODE7IS
BEGIN
PROCESS（NUM）
BEGIN
CASENUMIS
WHEN"0000"=>LOUT<="0111111";
WHEN"0001"=>LOUT<="0000110";
WHEN"0010"=>LOUT<="1011011";
WHEN"0011"=>LOUT<="1001111";
WHEN"0100"=>LOUT<="1100110";
WHEN"0101"=>LOUT<="1101101";
WHEN"0110"=>LOUT<="1111101";
WHEN"0111"=>LOUT<="0000111";
WHEN"1000"=>LOUT<="1111111";
WHEN"1001"=>LOUT<="1101111";
WHENOTHERS=>LOUT<="0000000";
ENDCASE;
ENDPROCESS;
ENDa;
decode7-2
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYDECODE7_2IS
PORT（
NUM:
INSTD_LOGIC_VECTOR（3DOWNTO0）;
LOUT:
OUTSTD_LOGIC_VECTOR（6DOWNTO0））;
ENDDECODE7_2;
ARCHITECTUREaOFDECODE7_2IS
BEGIN
LOUT<="0111111"WHENNUM="0000"ELSE
"0000110"WHENNUM="0001"ELSE
"1011011"WHENNUM="0010"ELSE
"1001111"WHENNUM="0011"ELSE
"1100110"WHENNUM="0100"ELSE
"1101101"WHENNUM="0101"ELSE
"1111101"WHENNUM="0110"ELSE
"0000111"WHENNUM="0111"ELSE
"1111111"WHENNUM="1000"ELSE
"1101111"WHENNUM="1001"ELSE
"0000000";
ENDa;
decode38-1
libraryieee;
useieee.std_logic_1164.all
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