基于verilog语言简易电子琴设计数字电子技术课程设计报告.docx
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基于verilog语言简易电子琴设计数字电子技术课程设计报告
数字电子技术课程设计报告
基于verilogHDL语言的简易电子琴设计
学院:
__信息与控制工程学院________
专业班级:
___电气11级四班______________
姓名:
___商玉玺________________________
学号:
___11053421_____________________
指导教师:
___________________________________
一、实验目的
1、学习verilogHDL语言的基本运用,能够利用其进行简单编程;
2、学习使用QuartusⅡ7.0的基本操作,能够利用其进行简单的设计;
3、结合实践加深对理论知识的理解。
二、设计题目
用verilogHDl语言设计简易电子琴。
三、题目要求
(1)单独从左至右按下S1-S7每个按键后能够各自对应发出“哆来咪发唆啦西”的音乐声;
(2)按下最右边按键(S8),同时再配合按下S1-S7键后,发高八度的对应音;
(3)按键需要进行“消抖”处理;
(4)外部输入脉冲信号频率为1mhz;
(5)扩展要求:
自主设计(增加低8度功能,自动播放一段音乐)。
四、设计原理
(1)喇叭的振动频率不同,导致产生不同的声音;振动频率越低,声音越低沉,振动频率越高,声音越尖锐。
题目中音乐基本音的“哆”对应频率为523Hz、“来”对应频率为587Hz、“咪”对应频率为659Hz、“发”对应频率为698Hz、“唆”对应频率为784Hz、“啦”对应频率为880Hz、“西”对应频率为998Hz。
低8度音:
基本音频率/2,例如低音1的频率为523/2=261.5Hz。
高8度音:
基本音频率×2,例如高音1的频率为523×2=1046Hz.。
不同的频率产生利用给定的时钟脉冲来进行分频实现。
(2)消抖的原理:
按键默认输入逻辑‘1’,当有按键按下时对应的输入为逻辑‘0’(但会存在抖动),当FPGA开始检测到该引脚从‘1’变为‘0’后开始定时(按键抖动时间大约10ms),定时时间结束后若该引脚仍然为‘0’则表示确实发生按键按下,否则视为抖动而不予以理会;按键松开过程的消抖处理和按下时原理一样。
(3)原理框图
四、管脚对应表
信号名称
对应FPGA管脚名
说明
1MHz
L2
基准时钟
OU
F3
音频输出
S1
F8
基本功能按键
S2
A14
S3
F10
S4
B16
S5
F12
S6
B17
S7
F15
S8
B18
BT1
M1
扩展功能按键
BT2
M2
BT3
U12
BT4
U11
五、实验过程
1、设计按键防抖模块
(1)设计程序
modulexiaodou(rst,clk_1M,out);
inputclk_1M;
inputrst;
outputout;
wirerst;
regout;
reg[24:
0]cnt;
reg[2:
0]state;
parameterstate0=3'b000,
state1=3'b001,
state2=3'b010,
state3=3'b011,
state4=3'b100,
state5=3'b101;
always@(posedgeclk_1M)
begin
cnt<=24'd0;
case(state)
state0:
if(!
rst)
begin
out=0;
state<=state1;
end
else
state<=state0;
state1:
begin
out=0;
cnt<=cnt+1;
if(cnt==10000)
state<=state2;
else
begin
//out=1;
state<=state1;
end
end
state2:
if(!
rst)
state<=state3;
else
state<=state0;
state3:
if(!
rst)
begin
out=1;
cnt<=0;
//state<=state3;
end
else
state<=state4;
state4:
begin
cnt<=cnt+1;
if(cnt==200000)
begin
out=1;
state<=state5;
end
else
begin
out=1;
state<=state4;
end
end
state5:
if(rst)
begin
out=0;
state<=state0;
end
else
state<=state3;
endcase
end
endmodule
(2)原理图及仿真波形
2、按键识别模块设计
(1)程序设计
modulexkey(a,b,c,d,e,f,g,h,l,qout);
inputa,b,c,d,e,f,g,h,l;
outputqout;
reg[8:
0]qin;
reg[4:
0]qout;
always@(aorborcordoreorforgorhorl)
begin
qin[8]=a;
qin[7]=b;
qin[6]=c;
qin[5]=d;
qin[4]=e;
qin[3]=f;
qin[2]=g;
qin[1]=h;
qin[0]=l;
end
always@(qin)
begin
case(qin)
9'b100000000:
qout<=5'b00001;
9'b010000000:
qout<=5'b00010;
9'b001000000:
qout<=5'b00011;
9'b000100000:
qout<=5'b00100;
9'b000010000:
qout<=5'b00101;
9'b000001000:
qout<=5'b00110;
9'b000000100:
qout<=5'b00111;
9'b100000010:
qout<=5'b01000;
9'b010000010:
qout<=5'b01001;
9'b001000010:
qout<=5'b01010;
9'b000100010:
qout<=5'b01011;
9'b000010010:
qout<=5'b01100;
9'b000001010:
qout<=5'b01101;
9'b000000110:
qout<=5'b01110;
9'b100000001:
qout<=5'b01111;
9'b010000001:
qout<=5'b10000;
9'b001000001:
qout<=5'b10001;
9'b000100001:
qout<=5'b10010;
9'b000010001:
qout<=5'b10011;
9'b000001001:
qout<=5'b10100;
9'b000000101:
qout<=5'b10101;
9'b000000000:
qout<=5'b00000;
9'b000000010:
qout<=5'b00000;
9'b000000001:
qout<=5'b00000;
default:
qout<=0;
endcase
end
endmodule
(2)原理图及仿真波形
3、分频器模块的设计
(1)程序设计
modulefenpin(in,clk_1M,out);
inputin;
inputclk_1M;
outputout;
wire[4:
0]in;
regout;
reg[11:
0]count;
reg[4:
0]state;
initial
count<=12'd0;
parameterstate0=5'b00000,
state1=5'b00001,
state2=5'b00010,
state3=5'b00011,
state4=5'b00100,
state5=5'b00101,
state6=5'b00110,
state7=5'b00111,
state8=5'b01000,
state9=5'b01001,
state10=5'b01010,
state11=5'b01011,
state12=5'b01100,
state13=5'b01101,
state14=5'b01110,
state15=5'b01111,
state16=5'b10000,
state17=5'b10001,
state18=5'b10010,
state19=5'b10011,
state20=5'b10100,
state21=5'b10101,
state22=5'b10110;
always@(posedgeclk_1M)
begin
case(state)
state0:
begin
//if(allin==5'b10110)
//state<=state0;
if(in==5'b00001)
state<=state1;
elseif(in==5'b00010)
state<=state2;
elseif(in==5'b00011)
state<=state3;
elseif(in==5'b00100)
state<=state4;
elseif(in==5'b00101)
state<=state5;
elseif(in==5'b00110)
state<=state6;
elseif(in==5'b00111)
state<=state7;
elseif(in==5'b01000)
state<=state8;
elseif(in==5'b01001)
state<=state9;
elseif(in==5'b01010)
state<=state10;
elseif(in==5'b01011)
state<=state11;
elseif(in==5'b01100)
state<=state12;
elseif(in==5'b01101)
state<=state13;
elseif(in==5'b01110)
state<=state14;
elseif(in==5'b01111)
state<=state15;
elseif(in==5'b10000)
state<=state16;
elseif(in==5'b10001)
state<=state17;
elseif(in==5'b10010)
state<=state18;
elseif(in==5'b10011)
state<=state19;
elseif(in==5'b10100)
state<=state20;
elseif(in==5'b10101)
state<=state21;
elseif(in==5'b00000)
state<=state22;
else
state<=state0;
end
state1:
begin
if(count<=956)
begin
begin
count=count+12'd1;
end
if(in==5'b00001)
state<=state1;
else
begin
out=0;
state<=state0;
end
end
else
begin
begin
out=~out;
count=0;
end
if(in==5'b00001)
state<=state1;
else
begin
out=0;
state<=state0;
end
end
end
state2:
beginif(count<=852)beginbegincount=count+12'd1;endif(in==5'b00010)state<=state2;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b00010)state<=state2;elsebeginout=0;state<=state0;endendend
state3:
beginif(count<=759)beginbegincount=count+12'd1;endif(in==5'b00011)state<=state3;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b00011)state<=state3;elsebeginout=0;state<=state0;endendend
state4:
beginif(count<=716)beginbegincount=count+12'd1;endif(in==5'b00100)state<=state4;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b00100)state<=state4;elsebeginout=0;state<=state0;endendend
state5:
beginif(count<=638)beginbegincount=count+12'd1;endif(in==5'b00101)state<=state5;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b00101)state<=state5;elsebeginout=0;state<=state0;endendend
state6:
beginif(count<=568)beginbegincount=count+12'd1;endif(in==5'b00110)state<=state6;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b00110)state<=state6;elsebeginout=0;state<=state0;endendend
state7:
beginif(count<=501)beginbegincount=count+12'd1;endif(in==5'b00111)state<=state7;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b00111)state<=state7;elsebeginout=0;state<=state0;endendend
state8:
beginif(count<=478)beginbegincount=count+12'd1;endif(in==5'b01000)state<=state8;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b01000)state<=state8;elsebeginout=0;state<=state0;endendend
state9:
beginif(count<=426)beginbegincount=count+12'd1;endif(in==5'b01001)state<=state9;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b01001)state<=state9;elsebeginout=0;state<=state0;endendend
state10:
beginif(count<=380)beginbegincount=count+12'd1;endif(in==5'b01010)state<=state10;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b01010)state<=state10;elsebeginout=0;state<=state0;endendend
state11:
beginif(count<=358)beginbegincount=count+12'd1;endif(in==5'b01011)state<=state11;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b01011)state<=state11;elsebeginout=0;state<=state0;endendend
state12:
beginif(count<=319)beginbegincount=count+12'd1;endif(in==5'b01100)state<=state12;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b01100)state<=state12;elsebeginout=0;state<=state0;endendend
state13:
beginif(count<=284)beginbegincount=count+12'd1;endif(in==5'b01101)state<=state13;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b01101)state<=state13;elsebeginout=0;state<=state0;endendend
state14:
beginif(count<=251)beginbegincount=count+12'd1;endif(in==5'b01110)state<=state14;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b01110)state<=state14;elsebeginout=0;state<=state0;endendend
state15:
beginif(count<=1912)beginbegincount=count+12'd1;endif(in==5'b01111)state<=state15;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b01111)state<=state15;elsebeginout=0;state<=state0;endendend
state16:
beginif(count<=1704)beginbegincount=count+12'd1;endif(in==5'b10000)state<=state16;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b10000)state<=state16;elsebeginout=0;state<=state0;endendend
state17:
beginif(count<=1518)beginbegincount=count+12'd1;endif(in==5'b10001)state<=state17;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b10001)state<=state17;elsebeginout=0;state<=state0;endendend
state18:
beginif(count<=1432)beginbegincount=count+12'd1;endif(in==5'b10010)state<=state18;elsebeginout=0;state<=state0;endend
elsebeginbeginout=~out;count=0;endif(in==5'b10010)state<=state18;elsebeginout=0;state<=state0;endendend
state19:
beginif(count<=1276)beginbegincount=count+12'd1;endif(in==5'b10011)state<=state19;elsebeginout=0;state<=state0;endend
elsebeginbegin