DAC芯片TLC5620verilog代码.docx

1、DAC芯片TLC5620verilog代码DAC芯片TLC5620-verilog代码DAC芯片TLC5620 Verilog代码 TLC5620是TI公司的DA转换芯片，下面的代码实现的简单的DA转换功能。说明：数码管1显示通道， 数码管2显示RNG值，数码管3和4显示CODE值。按键1切换通道，按键2改变RNG值(0或1)，按键3改变CODE值，按键4未使用。/* DAC11位数据输入说明:Bit10:9 通道选择00:CHA; 01:CHB; 10:CHC; 11:CHD Bit8 RNG 0:参考电压到地 1:两倍参考电压到地 Bit7:0 DAC转换代码，范围0255. 输出电压Vo

2、=REF*(CODE/256)*(1+RNG) */module dac( clk, rst_n, dac_clk, dac_data, dac_load, sw1_n,sw2_n,sw3_n,sw4_n, digit_o, cs );input clk; / 输入时钟50MHzinput rst_n; / 复位input sw1_n,sw2_n,sw3_n,sw4_n; / 按键 else low_sw_r = low_sw;wire3:0 led_ctrl = low_sw_r & (low_sw);reg 10:0 rData;always (posedge clk or negedge

3、 rst_n) if (!rst_n) rData = 11d255; else begin if (led_ctrl0 = 1) / S1键按下 rData10:9 = rData10:9 + 1b1; / 通道切换 if (led_ctrl1 = 1) / S2键按下 rData8 = rData8; / RNG位变化 if (led_ctrl2 = 1) / S3键按下 rData7:0 = rData7:0 + 8d8; / CODE变化 end/*/* DAC控制部分*/reg 5:0 div_cnt; / 分频计数器 64分频reg div_clk; / 分频时钟 注意不是DAC输

4、入时钟always (posedge clk or negedge rst_n)if (!rst_n) begin div_cnt = 6d0;div_clk = 1bz;endelse begin div_cnt = div_cnt + 1b1; if (div_cnt = 6d63) div_clk = 1b1; else div_clk = 1b0; end /*/reg 2:0 current_state,next_state;reg rDac_load;reg bit_cnt_rst; / 位计数器复位信号wire dat_send_done;always (posedge clk

5、or negedge rst_n) / 时序进程if (!rst_n) current_state = DAC_Idle;else current_state = next_state;always (current_state or div_clk or dat_send_done) begin / 组合进程rDac_load = 1b1;bit_cnt_rst = 1b0;next_state = DAC_Idle;case (current_state) DAC_Idle: begin bit_cnt_rst = 1b1; next_state = DAC_Send; / 空闲时直接进入

6、send状态end DAC_Send: begin if (dat_send_done) / 数据发送完成 next_state = DAC_Store; else next_state = DAC_Send;endDAC_Store: begin bit_cnt_rst = 1b1; rDac_load = 1b0; / LOAD变低进行锁存 if (div_clk) next_state = DAC_Idle; else next_state = DAC_Store;endendcaseend/*/reg 4:0 bit_cnt; / 位计数器 对div_clk计数always (pose

7、dge clk or negedge rst_n) beginif (!rst_n) bit_cnt = 5d0;else if (bit_cnt_rst) bit_cnt = 5d0;else if (div_clk) bit_cnt = bit_cnt + 1b1;endassign dat_send_done = (bit_cnt = 5d24);/*/reg rDac_data;always (bit_cnt4:1 or rData) begincase (bit_cnt4:1) / 从高到低发送11位数据 4d1 : rDac_data = rData10; 4d2 : rDac_d

8、ata = rData9; 4d3 : rDac_data = rData8; 4d4 : rDac_data = rData7; 4d5 : rDac_data = rData6; 4d6 : rDac_data = rData5; 4d7 : rDac_data = rData4; 4d8 : rDac_data = rData3; 4d9 : rDac_data = rData2; 4d10: rDac_data = rData1; 4d11: rDac_data = rData0; default : rDac_data = 2) & (bit_cnt 24) rDac_clk = b

9、it_cnt0; / 在时钟下降沿数据要有效else rDac_clk = 1b0;end/*/assign dac_clk = rDac_clk;assign dac_data = rDac_data;assign dac_load = rDac_load;/*/* 数码管显示部分* 说明:数码管1显示通道 数码管2显示RNG值* 数码管3和4显示CODE值*/reg 3:0 cs; / 片选信号reg 16:0 cnt2; / 计数寄存器2,确定扫描间隔reg 3:0 submsk; / 保存要显示的数据always (posedge clk or negedge rst_n)if (!r

10、st_n) begin cnt2 = 17d0; / 计数器2置零 cs = 4b0111; endelse begin cnt2 = cnt2 + 1b1; / 计数器2开始计数 if (cnt2 = 17d0) / 溢出了，又从0开始 begin if (cs = 4b0111) begin cs = 4b1110; / 选择第四个数码管 submsk = rData3:0; / 显示CODE低4位 end else if (cs = 4b1110) begin cs = 4b1101; / 选择第三个数码管 submsk = rData7:4; / 显示CODE高4位 end else

11、if (cs = 4b1101) begin cs = 4b1011; / 选择第二个数码管 submsk = 3b000,rData8; / 显示RNG值 end else if (cs = 4b1011) begin cs = 4b0111; / 选择第一个数码管 submsk = 2b00,rData10:9 + 1b1; / 显示通道 end end endreg 7:0 digit_o; / 数码管输出寄存器always (submsk)case (submsk) 4h0: digit_o = MSK_0; 4h1: digit_o = MSK_1; 4h2: digit_o = M

12、SK_2; 4h3: digit_o = MSK_3; 4h4: digit_o = MSK_4; 4h5: digit_o = MSK_5; 4h6: digit_o = MSK_6; 4h7: digit_o = MSK_7; 4h8: digit_o = MSK_8; 4h9: digit_o = MSK_9; 4hA: digit_o = MSK_A; 4hB: digit_o = MSK_B; 4hC: digit_o = MSK_C; 4hD: digit_o = MSK_D; 4hE: digit_o = MSK_E; 4hF: digit_o = MSK_F; default: digit_o = MSK_8; endcaseendmodule/ End