基于VHDL的通用计算器源程序文件.docx

1、基于VHDL的通用计算器源程序文件源程序4位二进制并行进位加法器的源程序 ADDER4B.VHD如下LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ADDER4B IS -四位二进制并行加法器 PORT(ci：IN STD_LOGIC; -低位进位a:IN STD_LOGIC_VECTOR3 DOWNTO 0); -4位加数b:IN STD_LOGIC_VECTOR(3 DOWNTO 0); -4位被加数s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -4位和

2、co:OUT STD_LOGIC -进位输出);END ADDER4B;ARCHITECTURE behave OF ADDER4B ISSIGNAL SINT:STD_LOGIC_VECTOR(4 DOWNTO 0); -部定义的一个数据SIGNAL aa，bb：STD_LOGIC_VECTOR(4 DOWNTO 0);BEGIN aa=0&a; -将4位加数矢量扩为5位，为进位提供空间 bb=0&b; -将4位被加数矢量扩为5位，为进位提供空间 INT=aa+bb+ci; - 相加 s=SINT(3 DOWNTO 0); coci,a=a(3 DOWNTO 0),b=b(3 DWONTO

3、0),s=(3 DOWNTO 0),co=CARRY_OUT); U2:ADDER4B -安装一个4位二进制加法器U2 PORT MAP(ci=CARRY_OUT,a=a(7 DOWNTO 4),b=b(7 DWONTO 4),s=(7 DOWNTO 4),co=co);END behave;加法器VHDL程序如下LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY adder IS port(a:in std_logic; -被加

4、数ab:in std_logic; -加数bci:in std_logic; -输入进位s:out std_logic; -结果输出co:out std_logic -输出进位);end adder;architecture behave of adder is signal tem: std_logic; -暂存signal stem: std_logic; begintem=a xor b; -中间变量stem=tem xor ci; -结果co=(tem and ci) or (a and b); -进位输出s=stem; -输出end behave;4位二进制并行进位减法器的源程序su

5、ber.VHD如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY sub4 IS PORT(a:IN STD_LOGIC_VECTOR(3 DOWNTO 0); -4位被减数b:IN STD_LOGIC_VECTOR(3 DOWNTO 0); -4位减数ci:IN STD_LOGIC; -输入进位s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -结果输出co:OUT STD_LOGIC -输出进位);

6、end suber;architecture behave of suber iscomponent adder is -引用加法器的模块 port(a:in std_logic; b:in std_logic; ci:in std_logic; s:out std_logic; co:out std_logic );end component;signal btem:std_logic_vector(3 downto 0); -减数寄存signal ctem:std_logic_vector(4 downto 0); - 进位寄存signal stem:std_logic_vector(3

7、downto 0); - 结果寄存beginbtem(3 downto 0)=not b(3 downto 0); -先把减数求反ctem(0)=not ci; -输入的进位也求反，从而对减数求补码g1:for I in 0 to 3 generate -连用4位全加器add:adder port map (a(i),btem(i),ctem(i),stem(i),ctem(i+1);end generate;s(3 downto 0)=stem(3 downto 0); -结果输出co=not ctem(4); -求反输出进位end behave;乘法器的源程序：LIBRARY IEEE;U

8、SE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;Entity mul is Port( a:in std_logic_vector(3 downto 0); -4位被乘数b:in std_logic_vector(3 downto 0); -4位乘数 y:out std_logic_vector(7 downto 0) -乘积）；end mul;architecture arch of mul isbeginy(7 downto 0) -开始状态if str=1 th

9、en -收到启动信号state=one; -转到状态oneatem(3 downto 0)=a(7 downto 4); -把高4位放到减法器被减数端 btem(3 downto 0)=b(3 downto 0); -把除数放到减法器减数端ain(7 downto 0)=a(7 downto 0); -寄存被除数bin(3 downto 0) -第一次移位if cotem=0 then -被除数高4位小于除数，溢出！state=eror; -转到出错状态else -不溢出ain(3 downto 1)=ain(2 downto 0); -被除数做移位ain(0)=not cotem; -在最低

10、位接收该位商值atem(3 downto 0)=ain(6 downto 3); -把除数寄存器高4位输到减法器，作为减法器被减数state -再做3此移位if n=2 then -第四次移位state=three; -是，则跳转到下一状态n:=0; -移位计数器清零else -否则 state=two; -还回到这个状态 n:=n+1; -移位计数器加1 end if; if cotem=0 then -不够减，有借位 atem(3 downto 1)=stem(2 downto 0); -减法器结果移位作为下一次的输入else -够减，没有借位 atem(3 downto 1)=atem(

11、2 downto 0); -结果输出移位作为下一次的输入end if; ain(3 downto 1)=ain(2 downto 0); -结果寄存器左移一位 ain(0)=not cotem; -这次运算借位输出，输入到寄存器ain最后一位 atem(0) -正常运算结果输出 s(3 downto 1)=ain(2 downto 0); -寄存器ain低3位作为输出结果高3位 s(0)=not cotem; -最后一次减法运算的借位输出求反作为结果输出最低位if cotem=0 then -最后一次减法运算，够减（无借位） y(3 downto 0)=atem(3 downto 0); -则

12、减法器输出结果为整个除法的余数else -否则，不够减 y(3 downto 0)=atem(3 downto 0); -则最后一次减法运算的被减数为整个除法的余数end if; atem(3 downto 0)= 0; -寄存器清零 btem(3 downto 0)= 0; -寄存器清零 state -溢出状态state=start; -回到开始状态atem(3 downto 0)= 0; -寄存器清零btem(3 downto 0)= 0; -寄存器清零end case;end if;end process p2;citem=0; -4位减法器借位输入接地U1:suber port map

13、(atem,btem,citem,stem,cotem);end behave; 数字按键译码电路VHDL语言描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity numdecoder isport(reset:in std_logic;inclk:std_logic;innum:std_logic_vetctor(9 downto 0);outnum:buffer std_logic_vector(3 woento 0);ou

14、tflag:out std_logic);end;architecture behave of numdecoer isbegin if reser=1then outnumoutnum=”0000”;outflagoutnum=”0001”;outflagoutnum=”0010”;outflagoutnum=”0011”;outflagoutnum=”0100”;outflagoutnum=”0101”;outflagoutnum=”0110”;outflagoutnum=”0111”;outflagoutnum=”1000”;outflagoutnum=”1001”;outflagout

15、num=outnum;outflag=0; -不按键时保持end case;end if;end process;end behave; 7段译码器的vhdl语言描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity vdecode isport(indata:in std_logic_vector(3 downto 0);outdata:out std_logic_vector(0 to 6);End;Atchitecture

16、behave of vdecode isBeginWith indata selectOutdata=”1111110”when”0000”, ”0110000”when”0000”,”1111001”when”0000”,”0110011”when”0000”,”1011011”when”0000”,”1011111”when”0000”,”1110000”when”0000”,”1111111”when”0000”,”1111110”when”0000”, ”1111110”when”0000”,”1111011”when”0000”,”0000000”when others;End be

17、have;8位二进制数转换成个位、十位、百位的进程：Ctrview:process(c,clk)Begin If c=1then view1=”0000”;view2=”0000”;view=”0000”;viewstepktemp=keep;viewstepif ktemp=”11001000”then view1=”0010”;ktemp=”01100100”then view1=”0001”;ktemp=ktemp-“01100100”;elsif view1=”0000”;end if; viewstepif ktemp=”01011010”thenview2=”1001”;ktemp

18、=”01010000”then view2=”1000”;ktemp=”01000110”then view2=”0111”;ktemp=”00111100”then view2=”0110”;ktemp=”00110010”then view2=”0101”;ktemp=”00101000”then view2=”0100”;ktemp=”00011110”then view2=”0011”;ktemp=”00010100”then view2=”0010”;ktemp=”00001010”then view2=”0001”;ktemp=ktemp-“00001010”;elsif view

19、2=”0000”;end if; viewstepview3=ktemp(3 downto 0);viewstepNULL;end case;end if;end process ctrview; 计算器的VHDL语言LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;Entity cal is Port(inclk:in std_logic; num:in std_logic_vector(9 downto 0); plus: in std_

20、logic; subt: in std_logic; mult: in std_logic; mdiv: in std_logic; equal: in std_logic; c: in std_logic; onum1,onum2,onum3:out std_logic_vector(0 to0) );end cal;architecture behave of cal istype state is(takenum,hundred,ten,one);signal viewstep: state;signal ktemp: std_logic_vector(7 downto 0);signa

21、l flag: std_logic;signal fl: std_logic;signal acc: std_logic_vector(7 downto 0);signalreg: std_logic_vector(7 downto 0);signal keep: std_logic_vector(7 downto 0);signal ans:std_logic_vector(7 downto 0);signal dans: std_logic_vector(3 downto 0);signal numbuff: std_logic_vector(3 downto 0);signal vf: std_logic;signal strdiv