国外经典Verilog代码.docx

1、国外经典Verilog代码/* * * Examples from The Verilog Hardware Description Language, * * by D.E. Thomas and P.R. Moorby * * */Example 1.2. NAND Latch To Be Simulated.module ffNand; wire q, qBar; reg preset, clear; nand #1 g1 (q, qBar, preset), g2 (qBar, q, clear); initial begin / two slashes introduce a sin

2、gle line comment $monitor ($time, Preset = %b clear = %b q = %b qBar = %b, preset, clear, q, qBar); /waveform for simulating the nand flip flop #10 preset = 0; clear = 1; #10 preset = 1; #10 clear = 0; #10 clear = 1; #10 $finish; endendmodule/Example 1.4. A 16-Bit Counter.module m16 (value, clock, f

3、ifteen, altFifteen); output 3:0 value; output fifteen, altFifteen; input clock; dEdgeFF a (value0, clock, value0), b (value1, clock, value1 value0), c (value2, clock, value2 &value1:0), d (value3, clock, value3 &value2:0); assign fifteen = value0 & value1 & value2 & value3; assign altFifteen = &valu

4、e;endmodule/Example 1.5. A D-Type Edge-Triggered Flip Flop.module dEdgeFF (q, clock, data); output q; reg q; input clock, data; initial q = 0; always (negedge clock) #10 q = data;endmodule/Example 1.6. A Clock For the Counter.module m555 (clock); output clock; reg clock; initial #5 clock = 1; always

5、 #50 clock = clock;endmodule/Example 1.7. The Top-Level Module of the Counter.module board; wire 3:0 count; wire clock, f, af; m16 counter (count, clock, f, af); m555 clockGen (clock); always (posedge clock) $display ($time,count=%d, f=%d, af=%d, count, f, af);endmodule/Example 1.8. The Counter Modu

6、le Described With Behavioral Statements.module m16Behav (value, clock, fifteen, altFifteen); output 3:0 value; reg 3:0 value; output fifteen, altFifteen; reg fifteen, altFifteen; input clock; initial value = 0; always begin (negedge clock) #10 value = value + 1; if (value = 15) begin altFifteen = 1;

7、 fifteen = 1; end else begin altFifteen = 0; fifteen = 0; end endendmodule/Example 1.9. Top Level of the Fibonacci Number Generator.module top(); wire flag, numProduced, numConsumed; wire 15:0 number, numberOut; nandLatch ready (flag, , numConsumed, numProduced); numberGen ng (number, numProduced, f

8、lag); fibNumberGen fng (number, flag, numConsumed, numberOut);endmodule/Example 1.10. A NAND Latch.module nandLatch (q, qBar, set, reset); output q, qBar; input set, reset; nand #2 (q, qBar, set), (qBar, q, reset);endmodule/Example 1.11. The Seed-Number Generator.module numberGen (number, numProduce

9、d, flag); output 15:0 number; output numProduced; input flag; reg numProduced; reg 15:0 number; initial begin number = 3; numProduced = 1; end always begin wait (flag = 1) #100 number = number + 1; numProduced = 0; #10 numProduced = 1; endendmodule/Example 1.12. The Fibonacci Number Generator Module

10、.module fibNumberGen (startingValue, flag, numConsumed, fibNum); input 15:0 startingValue; input flag; output numConsumed; output 15:0 fibNum; reg numConsumed; reg 15:0 myValue; reg 15:0 fibNum; initial begin numConsumed = 0; #10 numConsumed = 1; $monitor ($time, fibNum=%d, startingValue=%d, fibNum,

11、 startingValue); end always begin wait (flag = 0) myValue = startingValue; numConsumed = 0; #10 numConsumed = 1; /signal ready for input for (fibNum = 0; myValue != 0; myValue = myValue - 1) fibNum = fibNum + myValue; $display (%d, fibNum=%d, $time, fibNum); endendmodule/Example 2.1. A Divide Module

12、.module divide (ddInput, dvInput, quotient, go, done); parameter DvLen = 15, DdLen = 31, QLen = 15, HiDdMin = 16; input DdLen:0 ddInput; input DvLen:0 dvInput; output QLen:0 quotient; input go; output done; reg DdLen:0 dividend; reg done; reg QLen:0 quotient; reg negDivisor, negDividend; reg DvLen:0

13、 divisor; always begin done = 0; wait (go); divisor = dvInput; dividend = ddInput; quotient = 0; if (divisor) begin negDivisor = divisorDvLen; if (negDivisor) divisor = - divisor; negDividend = dividendDdLen; if (negDividend) dividend = - dividend; repeat (DvLen + 1) begin quotient = quotient 1; div

14、idend = dividend 1; dividendDdLen:HiDdMin = dividendDdLen:HiDdMin - divisor; if (! dividend DdLen) quotient = quotient + 1; else dividendDdLen:HiDdMin = dividendDdLen:HiDdMin + divisor; end if (negDivisor != negDividend) quotient = - quotient; end done = 1; wait (go); endendmodule/Example 2.5. The M

15、ark-1 Processor With If-Else-If.module mark1; reg 31:0 m 0:8191; / 8192 x 32 bit memory reg 12:0 pc; / 13 bit program counter reg 31:0 acc; / 32 bit accumulator reg 15:0 ir; / 16 bit instruction register always begin ir = m pc; /fetch an instruction if (ir15:13 = 3b000) /begin decoding pc = m ir 12:

16、0; /and executing else if (ir15:13 = 3b001) pc = pc + m ir 12:0; else if (ir15:13 = 3b010) acc = -m ir 12:0; else if (ir15:13 = 3b011) m ir 12:0 = acc; else if (ir15:13 = 3b101) | (ir15:13 = 3b100) acc = acc - m ir 12:0; else if (ir15:13 = 3b110) if (acc 0) pc = pc + 1; #1 pc = pc + 1; /increment pr

17、ogram counter and time end endmodule/Example 2.6. The Mark-1 With a Case Statement.module mark1Case; reg 31:0 m 0:8191; / 8192 x 32 bit memory reg 12:0 pc; / 13 bit program counter reg 31:0 acc; / 32 bit accumulator reg 15:0 ir; / 16 bit instruction register always begin ir = m pc; case (ir 15:13) 3

18、b000 : pc = m ir 12:0; 3b001 : pc = pc + m ir 12:0; 3b010 : acc = -m ir 12:0; 3b011 : m ir 12:0 = acc; 3b100, 3b101 : acc = acc - m ir 12:0; 3b110 : if (acc 0) pc = pc + 1; endcase pc = pc + 1; endendmodule/Example 2.8. The Mark-1 With a Multiply Instruction.module mark1Mult; reg 31:0 m 0:8191; / 81

19、92 x 32 bit memory reg 12:0 pc; / 13 bit program counter reg 31:0 acc; / 32 bit accumulator reg 15:0 ir; / 16 bit instruction register always begin ir = m pc; case (ir 15:13) 3b000 : pc = m ir 12:0; 3b001 : pc = pc + m ir 12:0; 3b010 : acc = -m ir 12:0; 3b011 : m ir 12:0 = acc; 3b100, 3b101 : acc =

20、acc - m ir 12:0; 3b110 : if (acc 0) pc = pc + 1; 3b111 : acc = acc * m ir 12:0; /multiply endcase #1 pc = pc + 1; endendmodule/Example 2.9. A Task Specification.module mark1Task; reg 31:0 m 0:8191; / 8192 x 32 bit memory reg 12:0 pc; / 13 bit program counter reg 31:0 acc; / 32 bit accumulator reg 15

21、:0 ir; / 16 bit instruction register always begin ir = m pc; case (ir 15:13) 3b000 : pc = m ir 12:0; 3b001 : pc = pc + m ir 12:0; 3b010 : acc = -m ir 12:0; 3b011 : m ir 12:0 = acc; 3b100, 3b101 : acc = acc - m ir 12:0; 3b110 : if (acc 1; mpy = mpy 1; end a = prod; end endtaskendmodule/Example 2.10.

22、A Function Specification.module mark1Fun; reg 31:0 m 0:8191; / 8192 x 32 bit memory reg 12:0 pc; / 13 bit program counter reg 31:0 acc; / 32 bit accumulator reg 15:0 ir; / 16 bit instruction register always begin ir = m pc; case (ir 15:13) 3b000 : pc = m ir 12:0; 3b001 : pc = pc + m ir 12:0; 3b010 :

23、 acc = -m ir 12:0; 3b011 : m ir 12:0 = acc; 3b100, 3b101 : acc = acc - m ir 12:0; 3b110 : if (acc 1; mpy = mpy 1; end endendfunctionendmodule/Example 2.11. The Multiply as a Separate Module.module mark1Mod; reg 31:0 m 0:8191; / 8192 x 32 bit memory reg 12:0 pc; / 13 bit program counter reg 31:0 acc;

24、 / 32 bit accumulator reg 15:0 ir; / 16 bit instruction register reg 31:0 mcnd; reg go; wire 31:0 prod; wire done; multiply mul (prod, acc, mcnd, go, done); always begin go = 0; ir = m pc; case (ir 15:13) 3b000 : pc = m ir 12:0; 3b001 : pc = pc + m ir 12:0; 3b010 : acc = -m ir 12:0; 3b011 : m ir 12:

25、0 = acc; 3b100, 3b101 : acc = acc - m ir 12:0; 3b110 : if (acc 1; myMpy = myMpy 1; end done = 1; wait (go); endendmodule/Example 3.4. Fibonacci Number Generator Using Named Events.module topNE(); wire 15:0 number, numberOut; numberGenNE ng(number); fibNumberGenNE fng(number, numberOut);endmodulemodule numberGenNE(number); output 15:0 number; re