乒乓球游戏机设计doc.docx

1、乒乓球游戏机设计docEDA课程论文设计乒乓球游戏机设计 学校：学院：班级：姓名：学号：指导教师：乒乓球游戏机设计一、实验目的：（1） 采用VHDL语言编写程序，并利用MAX+plusII对程序进行文本编辑输入、仿真测试并得出仿真波形,了解控制信号的时序。（2） 编写设计报告，要求包括方案选择、程序清单、调试过程、测试结果及心得体会。二、设计内容：用VHDL设计一个乒乓球游戏机，用开关来模拟球手及裁判，用LED来模拟乒乓球，采用每局十一球赛制，比分由七段显示器显示。采用按功能分块,将整个电路分成若干子程序,利用不同的子程序来实现记分、显示、键盘控制。三、设计原理： 1、设计步骤： （1）对4M

2、HZ信号进行分频,得到所需的1HZ,及七段显示器所需的频率.存为CLOCKMAKE.VHD(注:仿真时所加的信号频率比这要高。)。（2）设计一个子程序来描述裁判,左击球手,右击球手的动作对LED显示的影响,及失球后给出失球信号.这个程序是通过状态机来完成。存为LAYANGLED.VHD（3）利用上一子程序给出的矢球信号，来实现记分。并用按键来控制清零。DATACONTROL.VHD（4）从记分子程序得到分数，译码并动态显示出来。程序名为DATAGET.VHD及DISPLAY.VHD。（5）写主程序将上面的子程序组合起来。程序名为PINGPANGGAME.VHD。 按动开关JUDGE可以变动是由

3、哪边开始发球.球发出后,朝对方移去,如果对方接球过早,将使对方得一分,如果球到最近仍不击球,也将丢分,只有在球移动到最进处时,按动击打开关,球才会改变方向朝对方移去.选手每得一分,分数显示加一,满十一分时,局数加一.2、设计原理图： 四、实验设备：软件环境：MAX+PLUSCPLD软件开发系统，VHDL硬件描述语言五、设计程序:（1）顶层模块：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY pingpanggame ISPOR

4、T(clk_4mhz:IN STD_LOGIC; playr:IN STD_LOGIC; playl:IN STD_LOGIC; judge:IN STD_LOGIC; clr:IN STD_LOGIC; led:OUT STD_LOGIC_VECTOR(8 DOWNTO 0); tclr:IN STD_LOGIC; scan:OUT STD_LOGIC_VECTOR(5 downto 0); displaycode:OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );END pingpanggame;ARCHITECTURE play OF pingpanggame ISC

5、OMPONENT clockmake PORT (CLK : IN STD_LOGIC; CLK_DSP :OUT STD_LOGIC; CLK_1HZ :OUT STD_LOGIC );END COMPONENT;COMPONENT playandled PORT( clk: IN STD_LOGIC; playr: IN STD_LOGIC; playl: IN STD_LOGIC; judge: IN STD_LOGIC; led: OUT STD_LOGIC_VECTOR(9 DOWNTO 1); playrloss:OUT STD_LOGIC; playlloss:OUT STD_L

6、OGIC );END COMPONENT; COMPONENT display PORT( bcdin:IN STD_LOGIC_VECTOR(3 DOWNTO 0); displaycode:OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );END COMPONENT;COMPONENT dataget PORT(datain:IN STD_LOGIC_VECTOR(23 DOWNTO 0); clk_dsp:IN STD_LOGIC; scan: OUT STD_LOGIC_VECTOR(5 DOWNTO 0); bcdout: OUT STD_LOGIC_VECTOR

7、(3 DOWNTO 0) );END COMPONENT;COMPONENT datacontrol PORT( clk_1hz:IN STD_LOGIC; clr:IN STD_LOGIC; tclr:IN STD_LOGIC; playrloss:IN STD_LOGIC; playlloss:IN STD_LOGIC; data:OUT STD_LOGIC_VECTOR );END COMPONENT;SIGNAL clk_1hz:STD_LOGIC;SIGNAL clk_dsp:STD_LOGIC;SIGNAL bcdin:STD_LOGIC_VECTOR(3 DOWNTO 0);SI

8、GNAL playrloss:STD_LOGIC;SIGNAL playlloss:STD_LOGIC;SIGNAL data:STD_LOGIC_VECTOR(23 DOWNTO 0);SIGNAL bcdout: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINU1: clockmake PORT MAP(CLK=CLK_4MHZ,CLK_DSP=CLK_DSP,CLK_1HZ=CLK_1HZ);U5:playandled PORT MAP(playl=playl,playr=playr,judge=judge,clk=clk_1hz, led=led,playllos

9、s=playlloss,playrloss=playrloss);U6:datacontrol PORT MAP(clk_1hz=CLK_1HZ,clr=clr,tclr=tclr,playrloss=playrloss, playlloss=playlloss,data =data );U7:dataget PORT MAP(datain =data ,clk_dsp=clk_dsp,scan =scan ,bcdout =bcdout );U8:display PORT MAP(bcdin =bcdout ,displaycode=displaycode );END play(2) 子模块

10、一：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY playandled ISPORT( clk: IN STD_LOGIC; playr: IN STD_LOGIC; playl: IN STD_LOGIC; judge: IN STD_LOGIC; led: OUT STD_LOGIC_VECTOR(9 DOWNTO 1); playrloss:OUT STD_LOGIC; playlloss:OUT STD_LOGIC

11、);END ENTITY;-LB987654321RBARCHITECTURE behave OF playandled ISTYPE STATE IS(s9r,s8r,s7r,s6r,s5r,s4r,s3r,s2r,s1r,s9l,s8l,s7l,s6l,s5l,s4l,s3l,s2l,s1l,rloss,lloss,rb,lb,nop);SIGNAL ps:STATE;SIGNAL ns:STATE;BEGINclock:PROCESS(clk)BEGINIF(clkEVENT AND clk=1)THEN ps=ns;END IF;END PROCESS clock;statemachi

12、ne:PROCESS(ps,playr,playl,judge)BEGINIF(ps=lb)THEN IF(judge=0)THEN ns=rb; ELSIF(playl=0)THEN ns=s9r; ELSE ns=ps; END IF;ELSIF(ps=rb)THEN IF(judge=0)THEN ns=lb; ELSIF(playr=0)THEN ns=s1l; ELSE ns=ps; END IF;ELSIF(ps=s9r)THEN IF(judge=0)THEN ns=lb; ELSIF(playr=1)THEN ns=s8r; ELSE ns=rloss; END IF;ELSI

13、F(ps=s8r)THEN IF(judge=0)THEN ns=lb; ELSIF(playr=1)THEN ns=s7r; ELSE ns=rloss; END IF;ELSIF(ps=s7r)THEN IF(judge=0)THEN ns=lb; ELSIF(playr=1)THEN ns=s6r; ELSE ns=rloss; END IF;ELSIF(ps=s6r)THEN IF(judge=0)THEN ns=lb; ELSIF(playr=1)THEN ns=s5r; ELSE ns=rloss; END IF;ELSIF(ps=s5r)THEN IF(judge=0)THEN

14、ns=lb; ELSIF(playr=1)THEN ns=s4r; ELSE ns=rloss; END IF;ELSIF(ps=s4r)THEN IF(judge=0)THEN ns=lb; ELSIF(playr=1)THEN ns=s3r; ELSE ns=rloss; END IF;ELSIF(ps=s3r)THEN IF(judge=0)THEN ns=lb; ELSIF(playr=1)THEN ns=s2r; ELSE ns=rloss; END IF;ELSIF(ps=s2r)THEN IF(judge=0)THEN ns=lb; ELSIF(playr=1)THEN ns=s

15、1r; ELSE ns=rloss; END IF;ELSIF(ps=s1r)THEN IF(judge=0)THEN ns=lb; ELSIF(playr=1)THEN ns=rloss; ELSE ns=s2l; END IF;ELSIF(ps=s1l)THEN IF(judge=0)THEN ns=lb; ELSIF(playl=1)THEN ns=s2l; ELSE ns=lloss; END IF;ELSIF(ps=s2l)THEN IF(judge=0)THEN ns=lb; ELSIF(playl=1)THEN ns=s3l; ELSE ns=lloss; END IF;ELSI

16、F(ps=s3l)THEN IF(judge=0)THEN ns=lb; ELSIF(playl=1)THEN ns=s4l; ELSE ns=lloss; END IF;ELSIF(ps=s4l)THEN IF(judge=0)THEN ns=lb; ELSIF(playl=1)THEN ns=s5l; ELSE ns=lloss; END IF;ELSIF(ps=s5l)THEN IF(judge=0)THEN ns=lb; ELSIF(playl=1)THEN ns=s6l; ELSE ns=lloss; END IF;ELSIF(ps=s6l)THEN IF(judge=0)THEN

17、ns=lb; ELSIF(playl=1)THEN ns=s7l; ELSE ns=lloss; END IF;ELSIF(ps=s7l)THEN IF(judge=0)THEN ns=lb; ELSIF(playl=1)THEN ns=s8l; ELSE ns=lloss; END IF;ELSIF(ps=s8l)THEN IF(judge=0)THEN ns=lb; ELSIF(playl=1)THEN ns=s9l; ELSE ns=lloss; END IF;ELSIF(ps=s9l)THEN IF(judge=0)THEN ns=lb; ELSIF(playl=1)THEN ns=l

18、loss; ELSE ns=s8r; END IF;ELSIF(ps=rloss)THEN IF(judge=0)THEN ns=lb; ELSE ns=nop; END IF;ELSIF(ps=lloss)THEN IF(judge=0)THEN ns=lb; ELSE ns=nop; END IF;ELSIF(ps=nop)THEN IF(judge=0)THEN ns=lb; ELSE nsled=111111110;playlloss=0;playrlossled=011111111;playlloss=0;playrlossled=011111111;playlloss=0;play

19、rlossled=101111111;playlloss=0;playrlossled=110111111;playlloss=0;playrlossled=111011111;playlloss=0;playrlossled=111101111;playlloss=0;playrlossled=111110111;playlloss=0;playrlossled=111111011;playlloss=0;playrlossled=111111101;playlloss=0;playrlossled=111111110;playlloss=0;playrlossled=111111110;p

20、laylloss=0;playrlossled=111111101;playlloss=0;playrlossled=111111011;playlloss=0;playrlossled=111110111;playlloss=0;playrlossled=111101111;playlloss=0;playrlossled=111011111;playlloss=0;playrlossled=110111111;playlloss=0;playrlossled=101111111;playlloss=0;playrlossled=011111111;playlloss=0;playrloss

21、playlloss=1;ledplayrloss=1;ledled=111101111;playlloss=0;playrlossNULL;END CASE;END PROCESS translate;END behave;子模块二：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY datacontrol ISPORT(clk_1hz:IN STD_LOGIC; clr:IN STD_LOGIC; tclr:IN STD_LOG

22、IC; playrloss:IN STD_LOGIC; playlloss:IN STD_LOGIC; data:OUT STD_LOGIC_VECTOR(23 DOWNTO 0) );END datacontrol;ARCHITECTURE behave OF datacontrol ISSIGNAL lscore0,rscore0:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL lscore10,rscore10:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL ltotal,rtotal:STD_LOGIC_VECTOR(3 DOWNTO 0

23、);BEGINPROCESS(clk_1hz,clr,tclr,playrloss,playlloss)BEGINIF(tclr=0)THENrtotal=0000;ltotal=0000;ELSIF(clr=0)THENrscore0=0000;lscore0=0000;rscore10=0000;lscore10=0000;ELSIF(clk_1hzEVENT AND clk_1hz=1)THEN IF(playlloss=1)THEN IF(rscore09)THEN rscore0=rscore0+1; ELSE rscore0=0000; rscore10=0001; END IF;

24、 IF(rscore0=0000 AND rscore10=0001)THEN rscore0=0000; rscore10=0000; rtotal=rtotal+1; END IF; END IF; IF(playrloss=1)THEN IF(lscore09)THEN lscore0=lscore0+1; ELSE lscore0=0000; lscore10=0001; END IF; IF(lscore0=0000 AND lscore10=0001)THEN lscore0=0000; lscore10=0000; ltotal=ltotal+1; END IF; END IF;

25、END IF; END PROCESS;data(23 DOWNTO 20)=ltotal;data(19 DOWNTO 16)=lscore10;data(15 DOWNTO 12)=lscore0;data(11 DOWNTO 8)=rscore10;data(7 DOWNTO 4)=rscore0;data(3 DOWNTO 0)=rtotal;END behave;子模块三：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTIT

26、Y dataget ISPORT(datain:IN STD_LOGIC_VECTOR(23 DOWNTO 0); clk_dsp:IN STD_LOGIC; scan: OUT STD_LOGIC_VECTOR(5 DOWNTO 0); bcdout: OUT STD_LOGIC_VECTOR(0 TO 3) );END dataget;ARCHITECTURE behave OF dataget ISSIGNAL S: STD_LOGIC_VECTOR(2 DOWNTO 0):=000;BEGINU1:PROCESS(clk_dsp)BEGINIF(clk_dspEVENT AND clk_dsp=1)THENIF(S=4)THENS=S+1;ELSES bcdout=datain(3 downto 0); scan bcdout=datain(7 downto 4); scan bcdout=datain(11 downto 8); scan bc