实验四多周期CPU与存储器实验.docx

1、实验四多周期CPU与存储器实验湘潭大学实验报告 课程名称计算机原理与设计实验名称_多周期CPU与存储器实验 _ 页数 专业计算机科学与技术班级_2_同组者姓名 组别学号2015962138姓名庄振南实验日期_2016.11.02_ 一、实验目的 1、深入理解MIPSCPU指令系统的功能和工作原理；2、掌握多周期CPU的工作原理和逻辑功能实现；3、熟练掌握用Verilog HDL语言设计多周期存储器的方法；4、熟练掌握对多周期存储器的仿真实验验证和硬件测试两种调试方法；5、通过对多周期CPU的运行情况进行观察和分析，进一步加深理解。二、实验要求 1、深入理解MIPSCPU指令系统的功能和工作原理

2、；2、掌握多周期CPU的工作原理和逻辑功能实现；3、熟练掌握用Verilog HDL语言设计多周期存储器的方法；三、实验原理 实现上述原理框图根据功能将其分划分为控制单元(cunit)、执行单元(eunit)、指令单元(iunit)以及存储单元(munit)四大模块。 （1）.控制单元(cunit)是多周期微处理器的核心 控制微处理器取指令、指令译码和指令执行等工作。主要由指令译码器控制器(outputs control)、算术逻辑运算控制器(ALU control)两个子模块组成。 （2）.执行单元(eunit)主要由寄存器堆(registers)和算术逻辑单元(ALU)两个子模块组成。其中

3、寄存器是微处理器最基本的元素 MIPS系统的寄存器堆由32个32位寄存器组成 而ALU则是微处理器的主要功能部件 执行加、减、比较等算术运算和与、或、或非、异或等逻辑运算。指令单元(iunit)的作用是决定下一条指令的地址PC值 。 （3）.存储单元(munit)由存储器(memory)、指令寄存器(instruction register)和存储数据寄存器(memory data register)组成。四、实验内容 1、设计一个32位MIPS多周期CPU 具体的要求如下: 至少运行下列的6类32条MIPS指令。 （1）算术逻辑指令 and、sub、addi （2）逻辑运算指令 and、0r

4、、xor、 andi、 ori、xori（3）位移指令 sll、srl、sra（4）条件分支指令 beq、bne、（5）无条件跳转指令 j、jr （6）数据传送指令 lw、sw2.设计一个存储器五、实验环境与设备 电脑，电箱。六、实验代码设计（含符号说明） 寄存器元件代码：module regfile (rna,rnb,d,wn,we,clk,clrn,qa,qb); input 4:0 rna,rnb,wn; input 31:0 d; input we,clk,clrn; output 31:0 qa,qb; reg 31:0 register 1:31; /r1-r31 assign q

5、a = (rna = 0) ? 0 : registerrna; /read assign qb = (rnb = 0) ? 0 : registerrnb; /read always (posedge clk or negedge clrn) begin if (clrn = 0) begin /reset integer i; for (i=1; i32; i=i+1) registeri = 0; end else begin if (wn != 0) & (we = 1) /write registerwn = d; end endendmodule32位四选一选择器：module m

6、ux4x32 (a0,a1,a2,a3,s,y); input 31:0 a0,a1,a2,a3; input 1:0 s; output 31:0 y; function 31:0 select; input 31:0 a0,a1,a2,a3; input 1:0 s; case (s) 2b00: select = a0; 2b01: select = a1; 2b10: select = a2; 2b11: select = a3; endcase endfunction assign y = select (a0,a1,a2,a3,s);endmodule5位二选一选择器：module

7、 mux2x5 (a0,a1,s,y); input 4:0 a0,a1; input s; output4:0 y; assign y = s ? a1 : a0;endmodule32位二选一选择器：module mux2x32 (a0,a1,s,y); input 31:0 a0,a1; input s; output 31:0 y; assign y = s ? a1 : a0;endmodule存储器元件：module mcmem (clk, dataout, datain, addr, we, inclk, outclk); input 31:0 datain; input 31:

8、0 addr; input clk, we, inclk, outclk; output 31:0 dataout; wire write_enable = we & clk; lpm_ram_dq ram (.data(datain),.address(addr7:2),.we(write_enable),.inclock(inclk),.outclock(outclk),.q(dataout); defparam ram.lpm_width = 32; defparam ram.lpm_widthad = 6; defparam ram.lpm_indata = registered; d

9、efparam ram.lpm_outdata = registered; defparam ram.lpm_file = mcmem.mif; defparam ram.lpm_address_control = registered;endmodule控制部件：module mccu (op, func, z, clock, resetn, wpc, wir, wmem, wreg, iord, regrt, m2reg, aluc, shift, alusrca, alusrcb, pcsource, jal, sext, state); input 5:0 op, func; inpu

10、t z, clock, resetn; output reg wpc, wir, wmem, wreg, iord, regrt, m2reg; output reg 3:0 aluc; output reg 1:0 alusrcb, pcsource; output reg shift, alusrca, jal, sext; output reg 2:0 state; reg 2:0 next_state; parameter 2:0 sif = 3b000, / IF state sid = 3b001, / ID state sexe = 3b010, / EXE state smem

11、 = 3b011, / MEM state swb = 3b100; / WB state wire r_type,i_add,i_sub,i_and,i_or,i_xor,i_sll,i_srl,i_sra,i_jr; wire i_addi,i_andi,i_ori,i_xori,i_lw,i_sw,i_beq,i_bne,i_lui,i_j,i_jal; and(r_type,op5,op4,op3,op2,op1,op0); and(i_add,r_type, func5,func4,func3,func2,func1,func0); and(i_sub,r_type, func5,f

12、unc4,func3,func2, func1,func0); and(i_and,r_type, func5,func4,func3, func2,func1,func0); and(i_or, r_type, func5,func4,func3, func2,func1, func0); and(i_xor,r_type, func5,func4,func3, func2, func1,func0); and(i_sll,r_type,func5,func4,func3,func2,func1,func0); and(i_srl,r_type,func5,func4,func3,func2

13、, func1,func0); and(i_sra,r_type,func5,func4,func3,func2, func1, func0); and(i_jr, r_type,func5,func4, func3,func2,func1,func0); and(i_addi,op5,op4, op3,op2,op1,op0); and(i_andi,op5,op4, op3, op2,op1,op0); and(i_ori, op5,op4, op3, op2,op1, op0); and(i_xori,op5,op4, op3, op2, op1,op0); and(i_lw, op5,

14、op4,op3,op2, op1, op0); and(i_sw, op5,op4, op3,op2, op1, op0); and(i_beq, op5,op4,op3, op2,op1, op0); and(i_bne, op5,op4,op3, op2,op1, op0); and(i_lui, op5,op4, op3, op2, op1, op0); and(i_j, op5,op4,op3,op2, op1,op0); and(i_jal, op5,op4,op3,op2, op1, op0); wire i_shift; or (i_shift,i_sll,i_srl,i_sra

15、); always * begin / control signals dfault outputs: wpc = 0; / do not write pc wir = 0; / do not write ir wmem = 0; / do not write memory wreg = 0; / do not write register file iord = 0; / select pc as memory address aluc = 4bx000; / ALU operation: add alusrca = 0; / ALU input a: reg a or sa alusrcb

16、 = 2h0; / ALU input b: reg b regrt = 0; / reg dest no: rd m2reg = 0; / select reg c shift = 0; / select reg a pcsource = 2h0; / select alu output jal = 0; / not a jal sext = 1; / sign extend case (state) /- IF: sif: begin / IF state wpc = 1; / write pc wir = 1; / write IR alusrca = 1; / PC alusrcb =

17、 2h1; / 4 next_state = sid; / next state: ID end /- ID: sid: begin / ID state if (i_j) begin / j instruction pcsource = 2h3; / jump address wpc = 1; / write PC next_state = sif; / next state: IF end else if (i_jal) begin / jal instruction pcsource = 2h3; / jump address wpc = 1; / write PC jal = 1; /

18、 reg no = 31 wreg = 1; / save PC+4 next_state = sif; / next state: IF end else if (i_jr) begin / jr instruction pcsource = 2h2; / jump register wpc = 1; / write PC next_state = sif; / next state: IF end else begin / other instruction aluc = 4bx000; / add alusrca = 1; / PC alusrcb = 2h3; / branch off

19、set next_state = sexe; / next state: EXE end end /- EXE: sexe: begin / EXE state aluc3 = i_sra; aluc2 = i_sub | i_or | i_srl | i_sra | i_ori | i_lui ; aluc1 = i_xor | i_sll | i_srl | i_sra | i_xori | i_beq | i_bne | i_lui ; aluc0 = i_and | i_or | i_sll | i_srl | i_sra | i_andi | i_ori ; if (i_beq |

20、i_bne) begin / beq or bne instruction pcsource = 2h1; / branch address wpc = i_beq & z | i_bne & z; / write PC next_state = sif; / next state: IF end else begin / other instruction if(i_lw | i_sw) begin / lw or sw instruction alusrcb = 2h2; / select offset next_state = smem; / next state: MEM end el

21、se begin / other instruction if (i_shift) shift = 1; / shift instruction if (i_addi | i_andi | i_ori | i_xori | i_lui) alusrcb = 2h2; / select immediate if (i_andi | i_ori | i_xori) sext = 0; / 0-extend next_state = swb; / next state: WB end end end /- MEM: smem: begin / MEM state iord = 1; / memory

22、 address = C if (i_lw) begin next_state = swb; / next state: WB end else begin / store wmem = 1; / write memory next_state = sif; / next state: IF end end /- WB: swb: begin / WB state if (i_lw) m2reg = 1; / select memory data if (i_lw | i_addi | i_andi | i_ori | i_xori | i_lui) regrt = 1; / reg dest

23、 no: rt wreg = 1; / write register file next_state = sif; / next state: IF end /- END default: begin next_state = sif; /default state end endcase end always (posedge clock or negedge resetn) begin / state registers if (resetn = 0) begin state = sif; end else begin state = next_state; end endendmodul

24、e32位带使能端触发器：module dffe32 (d,clk,clrn,e,q); input 31:0 d; input clk,clrn,e; output 31:0 q; reg 31:0 q; always (negedge clrn or posedge clk) if (clrn = 0) begin q = 0; end else begin if(e = 1) q = d; endendmodule32位触发器：module dff32 (d,clk,clrn,q); input 31:0 d; input clk,clrn; output 31:0 q; reg 31:0 q; always (negedge clrn or posedge clk) if (clrn = 0) begin q = 0; end else begin q = d; endendmoduleALU计算部件：module alu (a,b,aluc,r,z); input 31:0 a,b; input 3:0 aluc; output 31:0 r; output z; assign r = cal(a,b,aluc); assign z = |r; function 31:0 cal;