JESD47I中文版.docx

1、JESD47I中文版IC集成电路压力测试考核NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the publi

2、c interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the stan

3、dard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume

4、 any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organi

5、zation there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to

6、the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to under Standards and Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2012 3103 North 10th Street Suite 240 South Arlington, VA 22201-21

7、07 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the All rights reserved PLEASE! DONT VIOLATE THE LAW! This docum

8、ent is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to under Standards-Documents/Copyright Information. STRESS DRIVEN QUALIFICATION OF INT

9、EGRATED CIRCUITS IC集成电路压力测试考核 (From JEDEC Board Ballot, JCB-12-24, formulated under the cognizance of the Subcommittee on Silicon Devices Reliability Qualification and Monitoring.) 通过JEDEC委员会JCB-12-24号投票，在硅晶圆器件可靠性考核和监控小组委员会审理后系统地阐述和制定1 Scope 范围 This standard describes a baseline set of acceptance te

10、sts for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed. 这个文档描述了用于考核新产品、同族器件或工艺变更的可接受的基准测试标准These tests are capable of stimulating and precipitating semiconductor device and packaging failures. The objective is to precipit

11、ate failures in an accelerated manner compared to use conditions. Failure Rate projections usually require larger sample sizes than are called out in qualification testing. For guidance on projecting failure rates, refer to JESD85 Methods for Calculating Failure Rates in Units of FITs. This qualific

12、ation standard is aimed at a generic qualification for a range of use conditions, but is not applicable at extreme use conditions such as military applications, automotive under-the-hood applications, or uncontrolled avionics environments, nor does it address 2nd level reliability considerations, wh

13、ich are addressed in JEP150. Where specific use conditions are established, qualification testing tailored to meet those specific requirements can be developed, using JESD94 that will result in a better optimization of resources. 这些测试用于加速和诱发半导体器件和封装的失效。目的是通过比使用环境相比加速的方式来促成失效。相比考核测试，失效率的预测需要更多的样品数量。如

14、果需要计算预期的失效率，请参考JESD85 Methods for Calculating Failure Rates in Units of FITs。本考核标准用于制定一系列适用于一般使用环境下的通用考核标准，而不是用于例如军工应用，汽车电子，或者不受控的航天电子等极端使用环境；同时本标准也不解决JEP150标准中提出的2nd等级可靠性问题。在确定具体使用条件的情况下，可以使用JESD94开发适合于满足这些特定要求的考核测试，从而更好地优化测试资源。This set of tests should not be used indiscriminately. Each qualificati

15、on project should be examined for: a) Any potential new and unique failure mechanisms. b) Any situations where these tests/conditions may induce invalid or overstress failures. 注意：不要不加选择地使用本文档中的测试。 应对每个考核项目进行确认：a）是否存在任何潜在的新的和独特的失效机制。b）任何测试或使用条件可能导致的失效或过应力失效情况。If it is known or suspected that failure

16、s either are due to new mechanisms or are uniquely induced by the severity of the test conditions, then the application of the test condition as stated is not recommended. Alternatively, new mechanisms or uniquely problematic stress levels should be addressed by building an understanding of the mech

17、anism and its behavior with respect to accelerated stress conditions (Ref. JESD91, “Method for Developing Acceleration Models for Electronic Component Failure Mechanisms” and JESD94, “Application Specific Qualification using Knowledge Based Test Methodology”). Consideration of PC board assembly-leve

18、l effects may also be necessary. For guidance on this, refer to JEP150, Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components. This document does not relieve the supplier of the responsibility to assure that a product meets the comp

19、lete set of its requirements. 如果已知或怀疑失效是由于新机制或者独特的严苛测试条件引起，则不建议使用本文档描述的测试条件。 作为一种选择，可以通过理解器件在加速应力条件下的失效机制和表现，来解决新的失效机制或独特的失效问题（参考JESD91，“电子元器件失效机制加速模型的研究方法”和JESD94，“基于测试方法学的特殊考核“）。必须需要考虑PCB板级封装的影响。 有关这方面的指导，请参阅JEP150，与SMT贴装元件相关的压力测试考核和失效机制。本文件并不免除供应商确保产品符合其全部要求的责任。 2 Reference documents 参考文件 The rev

20、ision of the referenced documents shall be that which is in effect on the date of the qualification plan. Military 军工级 MIL-STD-883, Test Methods and Procedures for Microelectronics MIL-PRF 38535 Industrial 工业级 UL94, Tests for Flammability of Plastic Materials for Parts in Devices and Appliances. AST

21、M D2863, Flammability of Plastic Using the Oxygen Index Method. IEC Publication 695, Fire Hazard Testing. J-STD-020, Joint IPC/JEDEC Standard, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface-Mount Devices. JP-001, Foundry Process Qualification Guidelines (Wafer Fabrica

22、tion Manufacturing Sites). JESD22 Series, Reliability Test Methods for Packaged Devices JESD46, Guidelines for User Notification of Product/process Changes by Semiconductor Suppliers. JESD69, Information Requirements for the Qualification of Silicon Devices. JESD74, Early Life Failure Rate Calculati

23、on Procedure for Electronic Components. JESD78, IC Latch-Up Test. JESD85, Methods for Calculating Failure Rates in Units of FITs. JESD86, Electrical Parameters Assessment. JESD94, Application Specific Qualification using Knowledge Based Test Methodology. JESD91, Methods for Developing Acceleration M

24、odels for Electronic Component Failure Mechanisms. JEP122, Failure Mechanisms and Models for Semiconductor Devices. JEP143, Solid State Reliability Assessment Qualification Methodologies. JEP150, Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface

25、-Mount Components. JESD201, Environmental Acceptance Requirements for Tin Whisker Susceptibility of Tin and Tin Alloy Surface Finishes JESD22A121, Test Method for Measuring Whisker Growth on Tin and Tin Alloy Surface Finishes 3 General requirements 通用要求 Objective 目标 The objective of this procedure i

26、s to ensure that the device to be qualified meets a generally accepted set of stress test driven qualification requirements. Qualification is aimed at components used in commercial or industrial operating environments. 本考核流程目的是确保器件能够通过一套通用的可接受的压力测试要求。主要考核目标是针对在商业或工业工作环境中使用的器件 Qualification family 同族

27、考核 While this specification may be used to qualify an individual component, it is designed to also qualify a family of similar components utilizing the same fabrication process, design rules, and similar circuits. The family qualification may also be applied to a package family where the constructio

28、n is the same and only the size and number of leads differs. Interactive effects of the silicon and package shall be considered in applying family designations. 虽然本规范用于单个器件的考核，但也可用于验证使用相同晶圆制造工艺，设计规则和相似电路设计的同族器件。同时也可以用于验证结构相同但只有尺寸和管脚数量不同的封装类别。 使用同族定义时应考虑硅晶圆和封装的相互作用。 Lot requirements 批次需求 Test samples

29、 shall comprise representative samples from the qualification family. Manufacturing variability and its impact on reliability shall be assessed. Where applicable the test samples will be composed of approximately equal numbers from at least three (3) nonconsecutive lots. Other appropriate means may

30、be used to evaluate manufacturing variability. Sample size and pass/fail requirements are listed in Tables 1-3. Tables A and B give guidance on translating pass/fail requirements to larger sample sizes. Generic data and larger sample sizes may be employed based upon a Chi Squared distribution using

31、a total percent defective at a 90% confidence limit for the total required lot and sample size. ELFR requirements shall be assessed at a 60% confidence level as shown in Table B. If a single unique and expensive component is to be qualified, a reduced sample size qualification may be performed using

32、 1/3 the sample size listed in the qualification tables. 测试样品应包含同族器件中的代表性样品， 需要评估生产波动性对可靠性的影响。 在适当的情况下，需要从至少三个非连续批次中抽取相同数量的样品，或者使用其他适合评估生产波动性的方法。 表1-3中列出了测试样本量和合格/不合格的要求。 表A和B给出了更大样本量情况下的合格/不合格要求。对于所有需要评估的批次和样品，可以基于卡方分布（90%可信度的总失效率），使用通用的数据和更大的样品数量。 ELFR要求按照表B所示的60可信度进行评估。如果要对一个独特且昂贵的器件进行考核评估，则可以使用考核表中列出的1/3样本量。 Production requ