EX1基于QUARTUS MODELSIM波形器仿真.docx

1、EX1基于QUARTUS MODELSIM波形器仿真实验M3-1 基于QUARTUS/MODELSIM 波形发生器仿真实验目的：采用第三方软件实现FPGA仿真。实验内容：将基于QUARTUS产生的方波，锯齿波，三角波等波形用MODELSIM进行仿真。实验素材：exwave目录下文件实验要求：按以下指导做出正弦波仿真后，将方波，锯齿波，三角波前、后仿真做出来QUARTUS MODELSIM 仿真准备1. 打开exwave的工程文件2. Asignment-device-eda tools setting-simulate-a) Tools name :MODELSIMb) Format for

2、output netlist:VHDLc) Output dirctory :simulation/modelsimd) 设置完毕，编译，退出第三方仿真软件MODELSIM准备1 安装仿真环境：MODELSIM se6.52 建立工程建立MODELSIM ALTERA库文件进入MODELSIM之后，在transcript窗键入如下命令即可建立名为cycloneii的modelsim ALTERA仿真文件。vlib cycloneii vmap cycloneii cycloneii vcom -work cycloneii c:/altera/80/quartus/eda/sim_lib/cy

3、cloneii_atoms.vhdvcom -work cycloneii c:/altera/80/quartus/eda/sim_lib/cycloneii_components.vhdvcom -work cycloneii c:/altera/80/quartus/eda/sim_lib/altera_mf_components.vhdvcom -work cycloneii c:/altera/80/quartus/eda/sim_lib/altera_mf.vhdvlib cycloneii vmap cycloneii cycloneii vcom -work cycloneii

4、 d:/altera/80/quartus/eda/sim_lib/cycloneii_atoms.vhdvcom -work cycloneii d:/altera/80/quartus/eda/sim_lib/cycloneii_components.vhdvcom -work cycloneii d:/altera/80/quartus/eda/sim_lib/altera_mf_components.vhdvcom -work cycloneii d:/altera/80/quartus/eda/sim_lib/altera_mf.vhd注：第一次在新建计算机上运行QUARTUS与MO

5、DELSIM时进行220model.vhd 是work.lpm_components路径要根据实际安装目录来定，有的计算机可能是d:/altera/80/quartus/eda/sim_lib/设计步骤1建立工程2 在project窗口导入wave.vho3 编译wave.vho文件其由QUARTUS生成4 建立测试台文件以WAVE.VHO为源生成并编辑WAVE_TB.VHD文件，仿真WAVE_TB文件图1 建立工程altera库仿真库放在modelsim安装目录下的cycloneii下，要映射cycloneii库到modelsim安装目录下的cycloneii。图2 建立altera仿真库图

6、3开始仿真选中SDF选项，导入延时文件*.sdo(后仿真)在transcript窗键入Vsimadd wave *Vsimrun 140us选择dout信号，选择format-analog，REDIX-UNSIGNED可以用analog（custom）改变数据范围等图4 前仿真结果附录1 源文件：见附录2测试台文件如下：LIBRARY cycloneiiLIBRARY ieee ; USE IEEE.STD_LOGIC_SIGNED.ALL;USE cycloneii.cycloneii_components.all ; USE ieee.std_logic_1164.all ; ENTITY

7、 wave_tb IS END ; - cyclone为MODELSIM中ALTERA库的名称ARCHITECTURE wave_tb_arch OF wave_tb IS SIGNAL dout : std_logic_vector (7 downto 0) ; SIGNAL dac_wr : std_logic ; SIGNAL dac_cs : std_logic ; SIGNAL switch : std_logic_vector (2 downto 0):=000 ; SIGNAL dac_ab : std_logic ; SIGNAL clk : std_logic:=0 ; CO

8、MPONENT wave PORT ( dout : out std_logic_vector (7 downto 0) ; dac_wr : out std_logic ; dac_cs : out std_logic ; switch : in std_logic_vector (2 downto 0) ; dac_ab : out std_logic ; clk : in std_logic ); END COMPONENT ; BEGIN DUT : wave PORT MAP ( dout = dout , dac_wr = dac_wr , dac_cs = dac_cs , sw

9、itch = switch , dac_ab = dac_ab , clk = clk ) ; process(clk) begin clk =not clk after 10 ns; end process;END ;附录2设计源文件LIBRARY IEEE, cycloneii;USE IEEE.STD_LOGIC_SIGNED.ALL;USE IEEE.std_logic_1164.all;USE cycloneii.cycloneii_components.all;ENTITY wave IS PORT ( dac_wr : OUT std_logic; clk : IN std_lo

10、gic; dac_cs : OUT std_logic; dac_ab : OUT std_logic; dout : OUT std_logic_vector(7 DOWNTO 0); switch : IN std_logic_vector(2 DOWNTO 0) );END wave;ARCHITECTURE structure OF wave ISSIGNAL gnd : std_logic := 0;SIGNAL vcc : std_logic := 1;SIGNAL devoe : std_logic := 1;SIGNAL devclrn : std_logic := 1;SIG

11、NAL devpor : std_logic := 1;SIGNAL ww_devoe : std_logic;SIGNAL ww_devclrn : std_logic;SIGNAL ww_devpor : std_logic;SIGNAL ww_dac_wr : std_logic;SIGNAL ww_clk : std_logic;SIGNAL ww_dac_cs : std_logic;SIGNAL ww_dac_ab : std_logic;SIGNAL ww_dout : std_logic_vector(7 DOWNTO 0);SIGNAL ww_switch : std_log

12、ic_vector(2 DOWNTO 0);SIGNAL inst|altsyncram_component|auto_generated|ram_block1a0_PORTAADDR_bus : std_logic_vector(5 DOWNTO 0);SIGNAL inst|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus : std_logic_vector(7 DOWNTO 0);SIGNAL clkclkctrl_INCLK_bus : std_logic_vector(3 DOWNTO 0);SIGN

13、AL inst2|clk1clkctrl_INCLK_bus : std_logic_vector(3 DOWNTO 0);SIGNAL inst4|Add1114_combout : std_logic;SIGNAL inst4|Add1117 : std_logic;SIGNAL inst4|Add1118_combout : std_logic;SIGNAL inst4|Add0357_combout : std_logic;SIGNAL inst4|Add0363_combout : std_logic;SIGNAL inst6|Add060_combout : std_logic;S

14、IGNAL inst6|Add061 : std_logic;SIGNAL inst6|Add062_combout : std_logic;SIGNAL inst6|Add063 : std_logic;SIGNAL inst6|Add064_combout : std_logic;SIGNAL inst6|Add065 : std_logic;SIGNAL inst6|Add066_combout : std_logic;SIGNAL inst6|Add067 : std_logic;SIGNAL inst6|Add068_combout : std_logic;SIGNAL inst2|

15、Add067 : std_logic;SIGNAL inst2|Add068_combout : std_logic;SIGNAL inst7|Mux0158_combout : std_logic;SIGNAL inst7|Mux154_combout : std_logic;SIGNAL inst7|Mux254_combout : std_logic;SIGNAL inst6|clk1regout : std_logic;SIGNAL inst4|Add0374_combout : std_logic;SIGNAL inst6|Equal041_combout : std_logic;S

16、IGNAL inst6|clk127_combout : std_logic;SIGNAL inst6|coun83_combout : std_logic;SIGNAL inst6|coun84_combout : std_logic;SIGNAL inst2|coun83_combout : std_logic;SIGNAL clkclkctrl_outclk : std_logic;SIGNAL clkcombout : std_logic;SIGNAL inst3|q2_combout : std_logic;SIGNAL inst3|qregout : std_logic;SIGNA

17、L inst7|Mux0156_combout : std_logic;SIGNAL inst5|num3312_combout : std_logic;SIGNAL inst5|num0_wirecell_combout : std_logic;SIGNAL inst5|num3313 : std_logic;SIGNAL inst5|num4314_combout : std_logic;SIGNAL inst5|num4315 : std_logic;SIGNAL inst5|num5316_combout : std_logic;SIGNAL inst5|num5317 : std_l

18、ogic;SIGNAL inst5|num6318_combout : std_logic;SIGNAL inst5|num7322_combout : std_logic;SIGNAL inst5|Equal052_combout : std_logic;SIGNAL inst5|num7323_combout : std_logic;SIGNAL inst5|num324_combout : std_logic;SIGNAL inst5|num6319 : std_logic;SIGNAL inst5|num7320_combout : std_logic;SIGNAL inst4|Les

19、sThan0102_combout : std_logic;SIGNAL inst4|LessThan0103_combout : std_logic;SIGNAL inst4|Add0377_combout : std_logic;SIGNAL inst4|Add0358 : std_logic;SIGNAL inst4|Add0359_combout : std_logic;SIGNAL inst4|Add0376_combout : std_logic;SIGNAL inst4|Add0360 : std_logic;SIGNAL inst4|Add0361_combout : std_

20、logic;SIGNAL inst4|Add0375_combout : std_logic;SIGNAL inst4|Add0362 : std_logic;SIGNAL inst4|Add0364 : std_logic;SIGNAL inst4|Add0365_combout : std_logic;SIGNAL inst4|Add0373_combout : std_logic;SIGNAL inst4|Add0366 : std_logic;SIGNAL inst4|Add0368 : std_logic;SIGNAL inst4|Add0369_combout : std_logi

21、c;SIGNAL inst4|Add0371_combout : std_logic;SIGNAL inst7|Mux0159_combout : std_logic;SIGNAL inst7|Mux0160_combout : std_logic;SIGNAL inst7|Mux0157_combout : std_logic;SIGNAL inst4|Add0367_combout : std_logic;SIGNAL inst4|Add0372_combout : std_logic;SIGNAL inst4|Add1105_cout : std_logic;SIGNAL inst4|A

22、dd1107 : std_logic;SIGNAL inst4|Add1109 : std_logic;SIGNAL inst4|Add1111 : std_logic;SIGNAL inst4|Add1113 : std_logic;SIGNAL inst4|Add1115 : std_logic;SIGNAL inst4|Add1116_combout : std_logic;SIGNAL inst7|Mux155_combout : std_logic;SIGNAL inst7|Mux156_combout : std_logic;SIGNAL inst7|Mux255_combout

23、: std_logic;SIGNAL inst7|Mux256_combout : std_logic;SIGNAL inst7|Mux354_combout : std_logic;SIGNAL inst4|Add1112_combout : std_logic;SIGNAL inst7|Mux355_combout : std_logic;SIGNAL inst7|Mux356_combout : std_logic;SIGNAL inst4|Add1110_combout : std_logic;SIGNAL inst2|Add060_combout : std_logic;SIGNAL

24、 inst2|coun84_combout : std_logic;SIGNAL inst2|Add061 : std_logic;SIGNAL inst2|Add063 : std_logic;SIGNAL inst2|Add064_combout : std_logic;SIGNAL inst2|Add062_combout : std_logic;SIGNAL inst2|Add065 : std_logic;SIGNAL inst2|Add066_combout : std_logic;SIGNAL inst2|Equal041_combout : std_logic;SIGNAL i

25、nst2|clk127_combout : std_logic;SIGNAL inst2|clk1regout : std_logic;SIGNAL inst2|clk1clkctrl_outclk : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita0combout : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita0COUT : std_logic;SIGNAL inst1|lp

26、m_counter_component|auto_generated|counter_comb_bita1combout : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita1COUT : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita2combout : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|coun

27、ter_comb_bita2COUT : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita3combout : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita3COUT : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita4combout : std_logic;SIGNAL i

28、nst1|lpm_counter_component|auto_generated|counter_comb_bita4COUT : std_logic;SIGNAL inst1|lpm_counter_component|auto_generated|counter_comb_bita5combout : std_logic;SIGNAL inst7|Mux454_combout : std_logic;SIGNAL inst7|Mux455_combout : std_logic;SIGNAL inst7|Mux456_combout : std_logic;SIGNAL inst4|Ad

29、d1108_combout : std_logic;SIGNAL inst7|Mux0161_combout : std_logic;SIGNAL inst7|Mux515_combout : std_logic;SIGNAL inst7|Mux516_combout : std_logic;SIGNAL inst4|Add1106_combout : std_logic;SIGNAL inst7|Mux615_combout : std_logic;SIGNAL inst7|Mux616_combout : std_logic;SIGNAL inst7|Mux731_combout : st

30、d_logic;SIGNAL inst4|temp0111_combout : std_logic;SIGNAL inst7|Mux732_combout : std_logic;SIGNAL inst5|num : std_logic_vector(7 DOWNTO 0);SIGNAL inst4|temp : std_logic_vector(7 DOWNTO 0);SIGNAL inst1|lpm_counter_component|auto_generated|safe_q : std_logic_vector(5 DOWNTO 0);SIGNAL inst2|coun : std_logic_vector(4 DOWNTO 0);SIGNAL