VHDL程序设计题.docx

1、VHDL程序设计题VHDL程序设计题四、编程题（共50 分）2、编写一个2输入与门的VHDL程序，请写出库、程序包、实体、构造体相关语句，将端口定义为标准逻辑型数据结构（本题 10分）LIBRARY IEEE;USE (2)ENTITY nand2 ISPORT (a b:IN STD_LOGIC; ( 4)END nan d2：(8)ARCHITECTURE nand2 1 OF nand2 ISBEGINy = a NAND b：-与 y =NOT( a AND b)等价END nan d2_1：3、根据下表填写完成一个 3-8线译码器的VHDL程序(16分)。LIBRARY IEEE：U

2、SE decoder_3_to_8 ISP ORT (a,b,c,g1,g2a,g2b:IN STD_LOGIC：y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)：END decoder_3_to_8：ARCHITECTURE rtl OF decoder_3_to_8 ISSIGNAL indata:STD_LOGIC_VECTOR (2 DOWNTO 0)：BEGINin data y y y y y y y y y = XXXXXXXX：END CASE：ELSEyEND IF：END PROCESS;END rtl;选週 Wt入二iZEIM1人蠟二yoyJyttyf

3、亡bA py2-y3 7Ty&X1XXXXI1 11J11IXX1XXXJ1I11111oXXXXXJ11Ii1 JJ1ooQQo0I111I0oOO1Q11T111JooOIo1o1I11110oD1 1111I01I1i1oo1oo1111o11TIoooI1I11011I0o11o11I1114II0o111111 ;11I04、三态门电原理图如右图所示，真值表如左图所示，请完成其 （本题14分）VHDL程序构造体部分。春7- 5三态ns值表S!抿输人控tel閱人數据播21|dinCJlXc1 E01011JLIBRARY IEEE;USE tri_gate ISP ORT(di n,e

4、 n:IN STD_LOGIC;dout : OUT STD_LOGIC);END tri_gate ;ARCHITECTURE zas OF tri_gate ISBEGINP ROCESS (di n,e n)BEGINIF (en =) THEN dout = din;ELSE dout = Z;END IF;END P ROCESS ;END zas ;四、编程题(共50 分)1、根据一下四选一程序的结构体部分，完成实体程序部分(本题 en tity MUX4 isporttin std logic vector(1 dow nto 0);8 分)S：d: in std logic v

5、ector(3 dow nto 0);y: out std logic (8)end MUX4;architecture behave of MUX4 is beginpro cess(s)beginif (s=00) the n y=d(0);elsif (s=01) then y=d(1);elsif (s=10) then y=d (2);elsif (s=11) then y=d (3);elsen ull; end if;end p rocess;end behave;)；end eight_tri;(6)architecture a of eight tri is(8)sig na

6、l sel: std_logic_vector(8 dow nto 0); begin sel=e n_& b;y= “ 000” when (sel= ” 100000001 ” )else” 100000010 ” whe n (sel= ” 100000100whe n (sel= ” 100001000when (se1=0010000 ” )else whe n (sel= ” 100100000001 ” when (sel=“ 010”“ 011”“100”“101”110 ” when (sel= ” 101000000“111” when (se1=0000000 ” )el

7、se( ”zzz ;end a;)else(10)4、图中给出了 4位逐位进位全加器，请完成其)else)else(12)else)else(14)(16)VHDL程序。（本题16分）library IEEE; use full_add isport (a,b: carr:sum:in std_logic_vector (3 dow nto 0); inout std_logic_vector (4 dow nto 0);out std_logic_vector (3 downto 0);end full_add;architecture full_add com pon ent adder

8、port (arch of full_add isa,b,c:carr:sum:in std_logic; inout std_logic; out std_logic);end component;end full_add_arch;四、编程（共50分）1、完成下图所示的触发器。（本题10分）port map (a(0),b(0),carr(0),carr(1),sum(0);port ma p(a(1),b(1),carr(1),carr(2),sum(1);library IEEE;use VposDff isport (CLK, CLR, D: in STD_LOGIC:Q, QN:

9、out STD_LOGIC );end Vp osDf;architecture Vpo sDff_arch of VposDff is beginpro cess ( CLK, CLR )beginQN =1;if CLR=1 the n Q = 0;elsif CLKeve nt and CLK=1 thenQ = D; QN = not D; 8 分end if;10分end process;end Vpo sDff_arch;2、完成以下4位全加器代码（本题 10分）library IEEE;use full_add isport (a.b:instd_logic_vector (3

10、dow nto 0);cin:instd_logic;cout:out std_logic;sum:outstd_logic_vector (3 dow nto 0)；end full_add;architecture full_add_ component adder port ( a.b.c:arch of full_add isincarr:sum:outoutstd_logic; std_logic;std_logic );end component;sig nal c1.c2.c3: std_logic;port map( a(0).b(0).ci n.c1.sum(0);port

11、map( a(1).b.c1.c2.sum(1);port map(a(2).b(2).c2.c3.sum(2):port map( a(3).b(3).c3.cout.sum(3);3、补充完整如下代码，使之完成 4状态不断循环。（本题10分）ARCHITECTURE arc OF ss IStype states is ( _ sig nal outc: states; BEGINP ROCESS(clk)BEGINIF reset=1 thenoutc outc outc outc outc outc =st0;END CASE;end if;END P ROCESS;END arc;4

12、、设计异或门逻辑：（本题20分） 如下异或门，填写右边的真值表。 （此项5 分）A-1YJABY00011 、101C 10其表达式可以表示为：（此项5分）这一关系图示如下:试编写完整的 VHDL代码实现以上逻辑。可以采用任何描述法。（此项10 分）library ieee;useen tity yihuo1 isport(yend yihuo1;architecture yihuo1_behavior of yihuo1 is beginp rocessbeginif aa,b :in std_logic; :out std_logic );ab)y：=a x(第or b;2种写法)=b t

13、hen y=0;elsy=1; end if; end pro Cess; ehavior;end yihuo1_b10分四、编程（共50分，除特殊声明，实体可只写出 PORT语句，结构体要写完整）1、用IF语句编写一个二选一电路，要求输入 a、b, sel为选择端，输出 q。（本题10分）En tity sel2 isPort (a,b : in std_logic; sel : in std_logic; q : out std_logic );End sel2;Architecture a of sel2 isbeginif sel = 0 the nq = a;elseq = b; e

14、nd if;end a;(9)(10)2、编写一个4位加法计数器 VHDL程序的进程（不必写整个结构框架），要求复位信号reset 低电平时计数器清零，变高后，在上升沿开始工作；输入时钟信号为 clk，输出为q。（本题10分）Process(reset,clk)beginif reset = 0 he nq = 0000”；elsif clk vent and clk = 0 the nq = q + 1; end if;end p rocess;(9)(10)3、填写完成一个8-3线编码器的真值表（5分），并写出其VHDL程序（10分）。8 -3线编码器真值表enby0y1y21000000

15、0000010000001000110000010001010000100001110001000010010010000010110100000011011110xxxxxxxx高阻态architecture a of eight_tri issig nal sel: std_logic_vector(8 dow nto 0); begin sel=e n & b;end a;4、根据已给出的全加器的 VHDL程序，试写出一个4位逐位进位全加器的 VHDL程序。（本 题15分）library IEEE;use adder isport (四、编程（共50分，除特殊声明，实体可只写出 PORT

16、语句，结构体要写完整）1、用IF语句编写一个四选一电路，要求输入 dOd3, s为选择端，输出 y。（本题10分）entity MUX4 isport（ in std_logic_vector(1 downto 0); in std_logic_vector(3 downto 0); out std_logic(8)(10)equ_tm p = 1; end if;elseequ_t mp = 1;end if;end pro cess;3、填写完成一个3-8线译码器的真值表（5分），并写出其VHDL程序（10分）。3-8译码器的真值表ena2a1a0y10000000000110010000

17、001010100000010010110000100011000001000011010010000011100100000011110xxx00000000);end tri_eight;architecture a of tri_eight issig nal sel: std_logic_vector (3 dow nto 0);beginsel(0) = a(0); sel(1) = a(1); sel(2) = a(2); sel(3) = en; with sel selecty = 00000001 whe n 1000,00000010 when 1001,00000100

18、whe n1010,00001000 whe n1011,00010000 whe n1100,00100000 whe n1101,01000000 whe n1110,whe n 1111,00000000 whe nothers;end a;(10)4、根据已给出的二-十（BCD） 分）进制优先权编码器功能表，试写出其 VHDL程序。（本题15二-十（BCD进制优先权编码器功能表输入输出I112131415161718I9Y3Y2Y1Y01111111111111XXXXXXXX00110XXXXXXX010111XXXXXX0111000XXXXX01111001XXXX0111110

19、10XXX0111111011XX01111111100X0111111111010111111111110en tity p rior isport(d : in std_logic_vector(9 dow nto 1);q : out std_logic_vector(3 downto 0) );(2)(4)end prior;architecture behavior of prior is beginprocess(d)beginif d = 1 then q = 1111;elsif d(9) = 0 then q = 0110;elsif d(8) = 0 then q = 0111;elsif d(7) = 0 then q = 1000;elsif d(6) = 0 then q = 1001;elsif d(5) = 0 then q = 1010;elsif d(4) = 0 then q = 1011;elsif d(3) = 0 then q = 1100;elsif d(2) = 0 then q = 1101;elsif d(1) = 0 then q = 1110;end if;end process;end behavior;