基于FPGA的VHDL语言m序列生成详解+源码.docx

1、基于FPGA的VHDL语言m序列生成详解+源码说 明 可控m序列产生器我分成四个小模块来做，M，M1，M2，M3分别对应为：m序列产生器、控制器、码长选择器、码速率选择器。一、M: m序列产生器 这是该设计的核心部分，原理就是设计一个通用m序列产生子单元，然后由外部选择器来写入码型，码长等参数，加以循环可连接成任意长度的m序列产生器，其子单元结构如下： 如上图，若N=15，就有15个这样的子单元首尾相接。注意：开头和结尾的两个子单元会有所不同，因为首单元需要输入初值，尾单元要进行直通反馈，在程序里请多留意。 图中，主要部件是一个D触发器，Q(N+1)为上一级输出；Q(N)既是本级输出；CP为选

2、择后的时钟脉冲；B(N)为本级参数选择控制；A(N)受控于B(N),决定本级输出Q(N)是否反馈（B(N)为1时反馈）； C（N）为本级反馈；C（N-1）为下一级反馈。具体原理参看m序列组成结构。 此外，本程序还加入了EN(发送控制)、RN(首单元置数)、SEL1(码长选择，即N的选择，N=2-15)、SEL2(码型选择，即正逆码选择)四个控制端，可满足设计要求。OP为码输出端。二、M1：控制器 控制器主要是将外部的序列发送控制信号STA转换为EN和RN两个控制信号。其中，EN与STA的波形基本一致，只是它与CP进行了同步处理；RN在EN为1的头一个脉冲周期里置高电平，以达到为序列发生器的首端

3、置数的目的。如果不清楚的话可以看一下它的模拟波形。（注意：STA要采用自锁定开关，高电平有效）三、M2：码长选择 序列的码长选择既是N值的选择，码长=2*N-1。核心就是一个计数器，可从2计到15。按一次PUSH就可以自动加一（注意：按键建议采用自弹跳按键，如过需要软件清除按键震颤的话，我再做发给你），没有0，1两个状态。如果需要的话还可以扩展7段数码管的接口，以显示N值。四、M3：码速率选择器 码的传输速率是靠CP来控制的，CP的频率就等于码元速率。这段程序包含一个倍频器，一个5分频的分频器，可把5MHZ的脉冲源CLK扩展成1MHZ和10MHZ。FSEL1、FSLE2、FSEL3分别在选择1

4、、5、10MHZ时为高电平，其余两个为低，建议采用3选1单刀单掷开关。 M1-LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CTRL ISPORT( CP,STA : IN STD_LOGIC; EN,RN : OUT STD_LOGIC );END CTRL;ARCHITECTURE a OF CTRL IS SIGNAL Q1,Q2 : STD_LOGIC;BEGIN PROCESS(CP) BEGIN IF CPeve

5、nt AND CP=1 THEN Q2=Q1; Q1=STA; END IF; END PROCESS; EN=Q1; RN=Q1 AND NOT Q2;END a;M2-LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNTER ISPORT( PUSH,EN,RST : IN STD_LOGIC; SEL1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END COUNTER;ARCHITECT

6、URE a OF COUNTER IS SIGNAL B,C : STD_LOGIC; SIGNAL QN : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(PUSH,C) BEGIN IF EN=0 THENIF C=1 THEN QN=”0010”; ELSEIF PUSHEVENT AND PUSH=1 THEN QN=QN+1; END IF; ELSE QN=QN; END IF; END PROCESS; B=1 WHEN QN=”0000” ELSE 0; C=B OR RST; SEL1=QN;END a;M3-LIBRARY IEEE;

7、USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY FP ISPORT( CLK,FSEL1,FSEL2,FSEL3 : IN STD_LOGIC; CP : OUT STD_LOGIC);END FP;ARCHITECTURE a OF FP IS SIGNAL Q1,Q2,Q3,RST : STD_LOGIC; SIGNAL M1,M5,M10 : STD_LOGIC; SIGNAL QN : STD_LOGIC_VECTOR(2 DOWNTO 0);

8、BEGIN BP1 : BLOCK BEGIN PROCESS(CLK,Q1) BEGIN IF Q1=1 THEN Q1=0 ELSEIF CLKEVENT AND CLK=1 THEN Q1=1; END IF; END PROCESS; END BLOCK BP1;BP2 : BLOCK BEGIN PROCESS(CLK,Q2) BEGIN IF Q2=1 THEN Q2=0 ELSEIF CLKEVENT AND CLK=0 THEN Q2=1; END IF; END PROCESS; END BLOCK BP2; FP : BLOCK BEGIN PROCESS(CLK,RST)

9、 BEGIN IF RST=1 THEN QN=”000”; ELSEIF CLKEVENT AND CLK=1 THEN QN=QN+1; END IF; END PROCESS; END BLOCK FP; Q3=Q1 OR Q2; RST=1 WHEN QN=”101” ELSE 0; M1=QN(2) AND FSEL1; M2=CLK AND FSEL2; M3=Q3 AND FSEL3; CP=M1 OR M2 OR M3;END a;M-LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;US

10、E IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY PN1 ISPORT( CP,SEL2,EN,RN : IN STD_LOGIC; SEL1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); OP : OUT STD_LOGIC );END PN1;ARCHITECTURE a OF PN1 IS SIGNAL Q, A,B,C : STD_LOGIC_VECTOR(14 DOWNTO 0); SIGNAL SEL : STD_LOGIC_VECTOR(4 DOWNTO 0);BEGIN SEL=SEL1&SEL2; PROCESS (CP,SEL

11、) BEGIN IF CPevent AND CP=1 THEN IF EN=0 THEN Q=000000000000000; OP=Q(0); ELSE Q(14)=C(14) OR RN; B C(0)=Q(0); B(1)=1; FOR I IN 1 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(0)=Q(0); B(14)=1; FOR I IN 1 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR

12、A(I); END LOOP; OP C(1)=Q(1); B(2)=1; B(7)=1; B(11)=1; FOR I IN 2 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(1)=Q(1); B(5)=1; B(9) =1; B(14) =1; FOR I IN 2 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(2) =Q(2); B(3) =1; B(5) =

13、1; B(6) =1; FOR I IN 3 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(2) =Q(2); B(11) =1; B(12) =1; B(14) =1; FOR I IN 3 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(3) =Q(3); B(4) =1; B(7) =1; B(9) =1; FOR I IN 4 TO 14 LOOP Q(I-1

14、)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(3) =Q(3); B(9) =1; B(11) =1; B(14) =1; FOR I IN 4 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(4) =Q(4); B(6) =1; FOR I IN 5 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP

15、; OP C(4) =Q(4); B(13) =1; FOR I IN 5 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(5) =Q(5); B(8) =1; FOR I IN 6 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(5) =Q(5); B(12) =1; FOR I IN 6 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B

16、(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(6) =Q(6); B(10) =1; FOR I IN 7 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(6) =Q(6); B(11) =1; FOR I IN 7 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(7) =Q(7); B(9) =1; B(10) =1; B(11)

17、 =1; FOR I IN 8 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(7) =Q(7); B(11) =1; B(12) =1; B(13) =1; FOR I IN 8 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(8) =Q(8); B(11) =1; FOR I IN 9 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(

18、I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(8) =Q(8); B(12) =1; FOR I IN 9 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(9) =Q(9); B(10) =1; FOR I IN 10 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(9) =Q(9); B(14) =1; FOR I IN 10 TO

19、 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(10) =Q(10); B(12) =1; FOR I IN 11 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(10) =Q(10); B(13) =1; FOR I IN 11 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LO

20、OP; OP C(11) =Q(11); B(12) =1; FOR I IN 12 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(11) =Q(11); B(14) =1; FOR I IN 12 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(12) =Q(12); B(13) =1; FOR I IN 13 TO 14 LOOP Q(I-1)=Q(I); A(I

21、)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(12) =Q(12); B(14) =1; FOR I IN 13 TO 14 LOOP Q(I-1)=Q(I); A(I)=Q(I) AND B(I); C(I)=C(I-1) XOR A(I); END LOOP; OP C(13) =Q(13); B(14) =1; Q(13)=Q(14); A(14)=Q(14) AND B(14); C(14)=C(13) XOR A(14); OP=Q(13); END CASE; END If; END IF; END PROCESS;END a;