Verilog HDL举例1.docx

1、Verilog HDL举例1组合逻辑设计 数据比较器/- compare.v -module compare(equal,a,b);input a,b;output equal; assign equal=(a=b)?1:0; /a等于b时，equal输出为1；a不等于b时， /equal输出为0。endmodule 测试模块源代码：timescale 1ns/1ns /定义时间单位。include ./compare.v /包含模块文件。在有的仿真调试环境中并不需要此语句。 /而需要从调试环境的菜单中键入有关模块文件的路径和名称module comparetest; reg a,b; wir

2、e equal; initial /initial常用于仿真时信号的给出。 begin a=0; b=0; #100 a=0; b=1; #100 a=1; b=1; #100 a=1; b=0; #100 $stop; /系统任务，暂停仿真以便观察仿真波形。 end compare compare1(.equal(equal),.a(a),.b(b); /调用模块。 endmodule 仿真波形（部分）：时序逻辑设计2分频器 / half_clk.v:module half_clk(reset,clk_in,clk_out);input clk_in,reset;output clk_out

3、;reg clk_out;always (posedge clk_in) begin if(!reset) clk_out=0; else clk_out=clk_out; endendmodule测试模块的源代码：/- clk_Top.v -timescale 1ns/100psdefine clk_cycle 50module clk_Top.vreg clk_in,reset;wire clk_out;always #clk_cycle clk_in = clk_in;initial begin clk_in = 0; reset = 1; #100 reset = 0; #100 re

4、set = 1; #10000 $stop; endhalf_clk half_clk(.reset(reset),.clk_in(clk_in),.clk_out(clk_out);endmodule仿真波形：利用条件语句实现较复杂的时序逻辑电路分频器将20M的时钟分频为500K的时钟。基本原理与1/2分频器是一样的，但是需要定义一个计数器，以便准确获得1/40分频模块源代码：/ - fdivision.v -module fdivision(RESET,F20M,F500K);input F20M,RESET;output F500K;reg F500K;reg 7:0j; always

5、(posedge F20M) if(!RESET) /低电平复位。 begin F500K = 0; j = 0; end else begin if(j=19) /对计数器进行判断，以确定F500K信号是否反转。 begin j = 0; F500K = F500K; end else j = j+1; endendmodule测试模块源代码：/- fdivision_Top.v -timescale 1ns/100psdefine clk_cycle 50module division_Top; reg F20M_clk,RESET;wire F500K_clk;always #clk_c

6、ycle F20M_clk = F20M_clk; initial begin RESET=1;F20M_clk =0;#100 RESET=0;#100 RESET=1;#10000 $stop; endfdivision fdivision (.RESET(RESET),.F20M(F20M_clk),.F500K(F500K_clk);endmodule仿真波形：设计时序逻辑时采用阻塞赋值与非阻塞赋值的区别通过分别采用阻塞赋值语句和非阻塞赋值语句的两个看上去非常相似的两个模块blocking.v和non_blocking.v来阐明两者之间的区别。模块源代码：/ - blocking.v

7、-module blocking(clk,a,b,c); output 3:0 b,c; input 3:0 a; input clk; reg 3:0 b,c; always (posedge clk) begin b = a; c = b; $display(Blocking: a = %d, b = %d, c = %d.,a,b,c); end endmodule/- non_blocking.v -module non_blocking(clk,a,b,c); output 3:0 b,c; input 3:0 a; input clk; reg 3:0 b,c; always (p

8、osedge clk) begin b = a; c = b; $display(Non_Blocking: a = %d, b = %d, c = %d.,a,b,c); end endmodule测试模块源代码：/- compareTop.v -timescale 1ns/100psinclude ./blocking.vinclude ./non_blocking.vmodule compareTop; wire 3:0 b1,c1,b2,c2; reg 3:0 a; reg clk; initial begin clk = 0; forever #50 clk = clk; end i

9、nitial begin a = 4h3; $display(_); # 100 a = 4h7; $display(_); # 100 a = 4hf; $display(_); # 100 a = 4ha; $display(_); # 100 a = 4h2; $display(_); # 100 $display(_); $stop; end non_blocking non_blocking(clk,a,b2,c2); blocking blocking(clk,a,b1,c1);endmodule仿真波形（部分）：用case语句描述的4选1数据选择器module mux4_1(ou

10、t,in0,in1,in2,in3,sel);output out;input in0,in1,in2,in3;input1:0 sel;reg out;always (in0 or in1 or in2 or in3 or sel) case(sel)2b00: out=in0;2b01: out=in1;2b10: out=in2;2b11: out=in3;default: out=2bx; endcaseendmodule同步置数，同步清零的计数器module count(out,data,load,reset,clk);output7:0 out;input7:0 data;inpu

11、t load,clk,reset;reg7:0 out;always (posedge clk)beginif (!reset) out = 8h00;else if (load) out = data;else out = out + 1;endendmodule用always语句实现组合逻辑电路简单的指令译码电路的设计示例。通过对指令的判断，对输入数据执行相应的操作，包括加、减、与、或和求反。/- alu.v -define plus 3d0define minus 3d1define band 3d2define bor 3d3define unegate 3d4module alu(o

12、ut,opcode,a,b);output7:0 out;reg7:0 out;input2:0 opcode;input7:0 a,b; /操作数。always(opcode or a or b) /电平敏感的always块begin case(opcode) plus: out = a+b; /加操作。 minus: out = a-b; /减操作。 band: out = a&b; /求与。 bor: out = a|b; /求或。 unegate: out=a; /求反。 default: out=8hx;/未收到指令时，输出任意态。 endcaseend endmodule 如果不使

13、用default或else对缺省项进行说明，则易生成意想不到的锁存器，这一点一定要加以注意。指令译码器的测试模块源代码：/- alu_Top.v -timescale 1ns/1nsinclude ./alu.vmodule alutest; wire7:0 out; reg7:0 a,b; reg2:0 opcode; parameter times=5; initial begin a=$random%256; /Give a radom number blongs to 0,255 . b=$random%256; /Give a radom number blongs to 0,255

14、. opcode=3h0; repeat(times) begin #100 a=$random%256; /Give a radom number. b=$random%256; /Give a radom number. opcode=opcode+1; end #100 $stop; end alu alu1(out,opcode,a,b);endmodule仿真波形（部分）： 用 begin-end 串行块产生信号波形timescale 10ns/1nsmodule wave1;reg wave;parameter cycle=10;initial begin wave=0;#(cyc

15、le/2) wave=1;#(cycle/2) wave=0;#(cycle/2) wave=1;#(cycle/2) wave=0;#(cycle/2) wave=1;#(cycle/2) $finish ;endendmodule用 fork-join 并行块产生信号波形timescale 10ns/1nsmodule wave2;reg wave;parameter cycle=5;initialfork wave=0;#(cycle) wave=1;#(2*cycle) wave=0;#(3*cycle) wave=1;#(4*cycle) wave=0;#(5*cycle) wave

16、=1;#(6*cycle) $finish;joinendmodule持续赋值方式定义的 2 选 1 多路选择器module MUX21_1(out,a,b,sel);input a,b,sel;output out;assign out=(sel=0)?a:b; endmodule2 选 1 多路选择器(else部分写全)module MUX21_2(out,a,b,sel);input a,b,sel;output out;reg out;always(a or b or sel) begin if(sel=0) out=a; else out=b; endendmodule隐含的锁存器m

17、odule buried_ff(c,b,a);output c;input b,a;reg c;always (a or b) begin if(b=1)&(a=1) c=a&b; endendmodule模为 60 的 BCD码加法计数器module count60(qout,cout,data,load,cin,reset,clk);output7:0 qout;output cout;input7:0 data;input load,cin,clk,reset;reg7:0 qout;always (posedge clk) begin if (reset) qout=0; else i

18、f(load) qout=data; else if(cin) begin if(qout3:0=9) /低位是否为9 begin qout3:0=0; /回0 if (qout7:4=5) qout7:4=0; /判断高位是否为5 else qout7:4=qout7:4+1; end else qout3:0=qout3:0+1; end endassign cout=(qout=8h59)&cin)?1:0;endmoduleBCD码七段数码管显示译码器module decode4_7(decodeout,indec);output6:0 decodeout;input3:0 indec

19、;reg6:0 decodeout;always (indec) begin case(indec) 4d0:decodeout=7b1111110; 4d1:decodeout=7b0110000; 4d2:decodeout=7b1101101; 4d3:decodeout=7b1111001; 4d4:decodeout=7b0110011; 4d5:decodeout=7b1011011; 4d6:decodeout=7b1011111; 4d7:decodeout=7b1110000; 4d8:decodeout=7b1111111; 4d9:decodeout=7b1111011;

20、 default: decodeout=7bx; endcase endendmodule用 casez 描述的数据选择器module mux_casez(out,a,b,c,d,select);output out;input a,b,c,d;input3:0 select;reg out;always (select or a or b or c or d)begincasez(select)4b?1: out = a;4b?10: out = b;4b?100: out = c;4b1000: out = d;endcaseendendmodule用 for 语句描述的七人投票表决器 m

21、odule voter7(pass,vote);output pass;input6:0 vote;reg2:0 sum;integer i;reg pass;always (vote)beginsum=0;for(i=0;i=6;i=i+1)if(votei) sum=sum+1;if(sum2) pass=1; /至少4人else pass=0;endendmodule用 for 语句实现 2 个 8 位数相乘module mult_for(outcome,a,b);parameter size=8;inputsize:1 a,b;output2*size:1 outcome;reg2*s

22、ize:1 outcome;integer i;always (a or b)beginoutcome=0;for(i=1; i=size; i=i+1)if(bi) outcome=outcome +(a (i-1);endendmodule用 repeat 实现 8 位二进制数的乘法module mult_repeat(outcome,a,b);parameter size=8;inputsize:1 a,b;output2*size:1 outcome;reg2*size:1 temp_a,outcome;regsize:1 temp_b;always (a or b)beginoutc

23、ome=0;temp_a=a;temp_b=b;repeat(size) begin if(temp_b1) /最低位为1，执行加法 outcome=outcome+temp_a; temp_a=temp_a1; /b右移1位 endendendmodule同一循环的不同实现方式module loop1;integer i;initialfor(i=0;i4;i=i+1)begin$display(i=%h,i);endendmodulemodule loop2;integer i;initial begini=0;while(i4)begin$display (i=%h,i);i=i+1;e

24、ndendendmodulemodule loop3;integer i;initial begini=0;repeat(4)begin$display (i=%h,i);i=i+1;endendendmodule输出i=?使用了include 语句的 16 位加法器（相对路径、绝对路径）include adder.vmodule adder16(cout,sum,a,b,cin);output cout;parameter my_size=16;outputmy_size-1:0 sum;inputmy_size-1:0 a,b;input cin;adder my_adder(cout,sum,a,b,cin);endmodule/adder子模块module adder(cout,sum,a,b,cin);parameter size=16;output cout;outputsize-1:0 sum;input cin;inputsize-1:0 a,b;assign cout,sum=a+b+cin;endmodule条件编译举例module compile(out,A,B);output out;input A,B;ifdef addassign out=A+B;elseassign out=A-B;endifendmodule