library ieee副本.docx

1、library ieee 副本蜗牛的染色体学院 电子设计自动化实验报告 姓名：吃一口羊羔肉 学 号：一口吃羊羔肉 班 级：吃羊羔肉一口 实验内容：多路波形发生器 指导教师： 羊羔肉吃一口 报告日期：多路波形发生器实验1.实验要求1.1.对输入时钟信号进行分频，实现三路互差120度的信号。1.2.实现输出信号的占空比例控制。其中clk ：输入时钟信号；reset：同步复位信号（低电平有效）；div ：输入分频控制信号（6n分频）；ctrl ：占空比例控制信号，其中 当ctrl=1时，占空比为1：1； 当ctrl=2时，占空比为1：2； 当ctrl=3时，占空比为2：1；A,B,C：三路输出信号。

2、2.设计思路2.1 clk ：时钟输入，设置为上升沿触发；2.2.reset：题目要求同步复位，故应将时钟输入作为reset 触发的必要条件。2.3.div ：题目要求为6分频，用二进制表示为 (110)2,(1100)2，（100100)2以此类推。当temp计 数是遇到上述数字便清零重新技术以实现6n分 频。2.4.ctrl ：占空比为三种，分别用（01）2，（10）2，（11） 2表示。然后用temp中3位0和1的个数比例 来控制占空比。占空比=1的个数/(0的个数+1 的个数) 又因为题目要求相位角互差120度，即三个输出 依次领先前一位4个输入字符。即若A(0)=1，则 B(4)=1

3、，C(8)=1。A(0)B(4)C(8)为同相位。2.5.temp: 声明三个变量，其中 temp为三位，分别对应于A，B，C。用于输出。 temp2与temp3用于计数分频。3.程序流程图4.源程序一library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity zonghe is port ( clk:in std_logic; aclk:out std_logic; bclk:out std_logic; cclk:out std_lo

4、gic; resetb:in std_logic; div:in std_logic_vector(1 downto 0); ctrl:in std_logic_vector(1 downto 0) );end zonghe;architecture behave of zonghe issignal tmp:std_logic; signal tmp1:std_logic; signal tmp2:std_logic; signal cnt0:integer range 0 to 5:=0; signal cnt1:integer range 0 to 11:=0; signal cnt2:

5、integer range 0 to 17:=0; signal cnt3:integer range 0 to 23:=0; begin process(clk,resetb,div,ctrl) begin if clkevent and clk=1 then if resetb=0 then cnt0=0; cnt1=0; cnt2=0; cnt3=0; tmp=0; tmp1=0; tmp2=0; elsif resetb=1 then cnt0=cnt0+1; cnt1=cnt1+1; cnt2=cnt2+1; cnt3 case div is when 00= case cnt0 i

6、s when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2=0;cnt0 case cnt1 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tm

7、p1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt1 case cnt2 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tm

8、p1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt2 case cnt3 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tm

9、p1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt3 case div is when 00= case cnt0 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=

10、0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt0 case cnt1 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;c

11、nt1 case cnt2 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=

12、1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt2 case cnt3 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=

13、0;tmp1=0;tmp2tmp=0;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2=0;cnt3 case div is when 00= case cnt0 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2

14、tmp=1;tmp1=1;tmp2=0;cnt0 case cnt1 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt1 case cnt2 is when 0=tmp=0;tmp1=1;tmp2tmp=0;

15、tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt2 case cnt3

16、 is when 0=tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=0;tmp1=1;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=0;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2tmp=1;tmp1=1;tmp2=0;cnt3tmp=0;tmp1=0;tmp2=0; end case; end if; end if; end process; aclk=tmp; bclk=tmp1; cclk=tmp2;end behave;7源程序二library ieee;use ieee.std_logic_116