1、FPGA交通灯实验报告交通灯实验报告一, 实验目的实现两路信号灯交替亮起,并利用两组数码管分别对两路信号进行倒计时。两路信号时间分别为:V:绿灯(30S) H:红灯(35S) 黄灯(5s) 绿灯(30S) 红灯(35S) 黄灯(5S)二, 实验步骤建立工程可在欢迎界面点击“Creat a New Project”进入工程建立界面,亦可关闭欢迎界面,点击菜单栏的“File”,点击“New Project Wizard”进入建立工程界面。右侧为建立工程界面,点击next。在此界面选定工程路径,取好工程名,点击“Next”。注意:路径中不能有中文,工程名也不能有中文。一直点击“Next”进入器件设置
2、界面,DE2-70开发工具采用的Cyclone II系列的EP2C70F896C6N。点击“Finish”,完成工程建立1、 点击“File”,点击“New” 选择“Verilog HDL”2, 点击主界面工具栏中的 选择“Verilog HDL” 3、写入verilog代码。代码如下:module traffic(Clk_50M,Rst,LedR_H,LedG_H,LedY_H,LedR_V,LedG_V,LedY_V,Seg7_VH,Seg7_VL,Seg7_HH,Seg7_HL,led15);parameter S1=2b00;parameter S2=2b01;parameter S3
3、=2b10;parameter S4=2b11;input Clk_50M,Rst;output LedR_H,LedG_H,LedY_H,LedR_V,LedG_V,LedY_V;output6:0 Seg7_VH,Seg7_VL,Seg7_HH,Seg7_HL;output led15;/-div for 1Hz-start-reg Clk_1Hz;reg 31:0 Cnt_1Hz;always(posedge Clk_50M or negedge Rst)begin if(!Rst) begin Cnt_1Hz=1; Clk_1Hz=25000000) begin Cnt_1Hz=1;
4、Clk_1Hz=Clk_1Hz; end else Cnt_1Hz=30) Cnt30=1; else Cnt30=5) Cnt30=1; else Cnt30=30) Cnt30=1; else Cnt30=5) Cnt30=1; else Cnt30=30) CntV=1; else CntV=5) CntV=1; else CntV=35) CntV=1; else CntV=35) CntH=1; else CntH=30) CntH=1; else CntH=5) CntH=1; else CntH29) begin CntDis7:4=3; CntDis3:019) begin C
5、ntDis7:4=2; CntDis3:09) begin CntDis7:4=1; CntDis3:0=CntVV - 10; end else CntDis29) begin CntDiss7:4=3; CntDiss3:019) begin CntDiss7:4=2; CntDiss3:09) begin CntDiss7:4=1; CntDiss3:0=CntHH - 10; end else CntDiss=30) begin state=5) begin state=30) begin state=5) begin state=S1; end default: begin stat
6、e=S1; end endcaseendalways(posedge Clk_1Hz)begin case(state) S1: begin stateH=S1; stateV=S1; end S2: begin stateH=S1; stateV=S2; end S3: begin stateH=S2; stateV=S3; end S4: begin stateH=S3; stateV=S3; end endcaseendalways(posedge Clk_50M or negedge Rst)begin if(!Rst) begin LedR_H=0; LedG_H=0; LedY_H
7、=0; LedR_V=0; LedG_V=0; LedY_V=0; end else begin case(state) S1: begin LedR_H=1; LedG_H=0; LedY_H=0; LedR_V=0; LedG_V=1; LedY_V=0; end S2: begin LedR_H=1; LedG_H=0; LedY_H=0; LedR_V=0; LedG_V=0; LedY_V=1; end S3: begin LedR_H=0; LedG_H=1; LedY_H=0; LedR_V=1; LedG_V=0; LedY_V=0; end S4: begin LedR_H=
8、0; LedG_H=0; LedY_H=1; LedR_V=1; LedG_V=0; LedY_V=0; end default: begin LedR_H=0; LedG_H=0; LedY_H=0; LedR_V=0; LedG_V=0; LedY_V=0; end endcase endendassign led15=state;endmodule module SEG7_LUT ( oSEG,iDIG );input 3:0 iDIG;output 6:0 oSEG;reg 6:0 oSEG;always (iDIG)begin case(iDIG) 4h1: oSEG = 7b111
9、1001; / -t- 4h2: oSEG = 7b0100100; / | | 4h3: oSEG = 7b0110000; / lt rt 4h4: oSEG = 7b0011001; / | | 4h5: oSEG = 7b0010010; / -m- 4h6: oSEG = 7b0000010; / | | 4h7: oSEG = 7b1111000; / lb rb 4h8: oSEG = 7b0000000; / | | 4h9: oSEG = 7b0011000; / -b- 4ha: oSEG = 7b0001000; 4hb: oSEG = 7b0000011; 4hc: o
10、SEG = 7b1000110; 4hd: oSEG = 7b0100001; 4he: oSEG = 7b0000110; 4hf: oSEG = 7b0001110; 4h0: oSEG = 7b1000000; endcaseendendmodule编译工程保存文件,将文件放在所建工程所在路径下点击主界面工具栏中的图标也可点击菜单栏中“Processing”,点击“Start Compilation”分配关键如下:Clk_50M Input PIN_AD15 LedG_H Output PIN_AD9 LedG_V Output PIN_AJ6 LedR_H Output PIN_AJ7
11、 )LedR_V Output PIN_AJ5 )LedY_H Output PIN_AD8 LedY_V Output PIN_AK5 Rst Input PIN_AA23 Seg7_HH6 Output PIN_G1 Seg7_HH5 Output PIN_H3Seg7_HH4 Output PIN_H2 Seg7_HH3 Output PIN_H1 Seg7_HH2 Output PIN_J2 Seg7_HH1 Output PIN_J1 Seg7_HH0 Output PIN_K3 Seg7_HL6 Output PIN_E4 Seg7_HL5 Output PIN_F4 Seg7_H
12、L4 Output PIN_G4 Seg7_HL3 Output PIN_H8 Seg7_HL2 Output PIN_H7 Seg7_HL1 Output PIN_H4 Seg7_HL0 Output PIN_H6 Seg7_VH6 Output PIN_AD17 Seg7_VH5 Output PIN_AF17 7 Seg7_VH4 Output PIN_AE17 7 Seg7_VH3 Output PIN_AG16 Seg7_VH2 Output PIN_AF16 7 Seg7_VH1 Output PIN_AE16 7 Seg7_VH0 Output PIN_AG13 Seg7_VL6
13、 Output PIN_AD12 Seg7_VL5 Output PIN_AD11 Seg7_VL4 Output PIN_AF10 8 Seg7_VL3 Output PIN_AD10 Seg7_VL2 Output PIN_AH9 8 Seg7_VL1 Output PIN_AF9 8 Seg7_VL0 Output PIN_AE8 8 烧写代码在管脚配置完成后,还需将工程再编译一次,成功后,点击主界面工具栏中的亦可点击主界面菜单栏中“Tools”,点击“Programmer”进入代码烧写界面后,点击“Start”,当“Progress”为100%时,表示烧写完成,这是可观察DE2-70板现象获得预期的效果,两组的信号红黄绿灯交替切换,计数器记为零时信号灯切换状态,红灯35s,黄灯5s,绿灯30s。三, 心得体会通过本次实验初步了解了EDA技术,熟悉了FPGA开发板的开发流程,锻炼了动手能力。
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