显示器件驱动实验报告.docx

1、显示器件驱动实验报告西安邮电大学显示器件驱动实验报告院系 电子工程学院 班级 光电1103班学号 05114093（24） 姓名 张娟娟实验10使用FPGA驱动16*16 led点阵汉字滚动显示（四学时）一、 实验目的 1、了解FPGA和FPGA开发板的功能。 2、使用ALTERA公司的QuartusII进行开发和下载。 3、使用fpga开发板驱动16*16 led点阵，上下滚动显示汉字，左右滚动一句话。理解串并转换，分时复用，动态扫描的驱动原理。实现一句话左向右滚动。注意：fpga开发板上5根数据管脚和2根电源管脚要和16*16点阵驱动板通过杜邦线一一对应连接，使用杜邦头防止短路。二、 实验

2、所用仪表及主要器材 开发板，一台装有QuartusII软件的电脑，数据传输线。三、 实验原理简述 1.16*16静态显示一个汉字：严 方案一：行扫描；显示第一行的过程： 显示第一行： 1.1.将第一行行线（com线）置高（164电平经8550反向），即164输出的对应QA脚输出低电平。其它行线置低。即164输出的其它15个Q脚输出高电平。 1.2.将列线(seg线)置相应的显示码。显示码由16位组成，对应16根列线的值，列线值（显示码）由两个字节来表示。每个字节8位，代表8列，从第一行开始显示；并关闭其他行；然后第二行显示；并关闭其他行。第三行第十六行 第一行，第二行第十六行如此周而复始,由于

3、扫描频率很快，所以人眼视觉暂留效应，会感觉16行都被显示了，并且显示不同的内容。实际上任何时刻只点亮了一行。2.汉字取模3.取模软件的用法四、 实验结果记录（如输出波形，显示结果等） 五、 主要源代码amodule hanzi1(mainclk,rst,DATA,SRCK,RCK,AB,CLK);input mainclk,rst;output DATA,SRCK,RCK,AB,CLK;reg10:0 count;wire clk_24;reg3:0 state;reg3:0 cnt_164,cnt_595;reg15:0 temp;/reg4:0 cnt_c;reg14:0 delay_16

4、4;reg13:0 delay_595;reg SRCK,RCK,AB,CLK,DATA;reg 15:0 table115:0;reg 3:0 sel;reg 26:0 count1;reg 2:0state1;/0x00,0x80,0xF8,0x88,0x08,0x8C,0x08,0x90,0x78,0xA0,0x40,0xC0,0x40,0x80,0x43,0xFE,/0xF8,0xA0,0x48,0xA0,0x08,0x90,0x08,0x90,0x08,0x88,0x08,0xA6,0x29,0xC4,0x10,0x80,/*张,0*/0x7E,0xFC,0x22,0x44,0x12

5、,0x24,0x0A,0x14,0x12,0x24,0x29,0x44,0x0C,0x80,0x1F,0xFC,/0x10,0x80,0x3F,0xFC,0x50,0x80,0x1F,0xFC,0x10,0x80,0x10,0x80,0x1F,0xFE,0x10,0x00,/*翟,0*/always (posedge mainclk) count1=count1=49999999 ? 0 :count1+1;always (posedge mainclk) begin if(count1=49999999) state1=state1=5 ? 0 : state1+1; else state1

6、=state1; end/0x01,0x00,0x21,0x10,0x19,0x18,0x0D,0x10,0x09,0x20,0x01,0x04,0x7F,0xFE,0x04,0x40,/0x04,0x40,0x04,0x40,0x04,0x40,0x08,0x42,0x08,0x42,0x10,0x42,0x20,0x3E,0x40,0x00,/*光,0*/always (state1) begin if(state1=0) begin table10=16h0100; table11=16h2110; table12=16h1918; table13=16h0d10; table14=16

7、h0920; table15=16h0104; table16=16h7ffe; table17=16h0440; table18=16h0440; table19=16h0440; table110=16h0440; table111=16h0842; table112=16h0842; table113=16h1042; table114=16h203e; table115=16h4000; end/0x01,0x00,0x01,0x00,0x01,0x00,0x3F,0xF8,0x21,0x08,0x21,0x08,0x3F,0xF8,0x21,0x08,/0x21,0x08,0x21,

8、0x08,0x3F,0xF8,0x21,0x08,0x01,0x02,0x01,0x02,0x00,0xFE,0x00,0x00,/*电,0*/ else if(state1=1) begin table10=16h0100; table11=16h0100; table12=16h0100; table13=16h3FF8; table14=16h2108; table15=16h2108; table16=16h3FF8; table17=16h2108; table18=16h2108; table19=16h2108; table110=16h3FF8; table111=16h210

9、8; table112=16h0102; table113=16h0102; table114=16h00FE; table115=16h0000; end/0x00,0x80,0xF8,0x88,0x08,0x8C,0x08,0x90,0x78,0xA0,0x40,0xC0,0x40,0x80,0x43,0xFE,/0xF8,0xA0,0x48,0xA0,0x08,0x90,0x08,0x90,0x08,0x88,0x08,0xA6,0x29,0xC4,0x10,0x80,/*张,2*/ else if(state1=2) begin table10=16h0080; table11=16h

10、F888; table12=16h088C; table13=16h0890; table14=16h78A0; table15=16h40C0; table16=16h4080; table17=16h43FE; table18=16hF8A0; table19=16h48A0; table110=16h0890; table111=16h0890; table112=16h0888; table113=16h08A6; table114=16h29C4; table115=16h1080; end/0x7E,0xFC,0x22,0x44,0x12,0x24,0x0A,0x14,0x12,0

11、x24,0x29,0x44,0x0C,0x80,0x1F,0xFC,/0x10,0x80,0x3F,0xFC,0x50,0x80,0x1F,0xFC,0x10,0x80,0x10,0x80,0x1F,0xFE,0x10,0x00,/*翟,3*/ else if(state1=3) begin table10=16h7EFC; table11=16h2244; table12=16h1224; table13=16h0A14; table14=16h1224; table15=16h2944; table16=16h0C80; table17=16h1FFC; table18=16h1080;

12、table19=16h3FFC; table110=16h5080; table111=16h1FFC; table112=16h1080; table113=16h1080; table114=16h1FFE; table115=16h1000; end/0x01,0x08,0x10,0x8C,0x0C,0xC8,0x08,0x90,0x7F,0xFE,0x40,0x04,0x8F,0xE8,0x00,0x40,/0x00,0x80,0x7F,0xFE,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x02,0x80,0x01,0x00,/*学,4*/ el

13、se if(state1=4) begin table10=16h0108; table11=16h108C; table12=16h0CC8; table13=16h0890; table14=16h7FFE; table15=16h4004; table16=16h8FE8; table17=16h0040; table18=16h0080; table19=16h7FFE; table110=16h0080; table111=16h0080; table112=16h0080; table113=16h0080; table114=16h0280; table115=16h0100;

14、end/0x00,0x80,0xF8,0x40,0x8F,0xFE,0x94,0x04,0xA0,0x00,0xA3,0xF8,0x90,0x00,0x88,0x00,/0x8F,0xFE,0xA9,0x20,0x91,0x20,0x81,0x20,0x82,0x22,0x82,0x22,0x84,0x22,0x88,0x1E,/*院,5*/ else if(state1=5) begin table10=16h0080; table11=16hF840; table12=16h8FFE; table13=16h9404; table14=16hA000; table15=16hA3F8; t

15、able16=16h9000; table17=16h8800; table18=16h8FFE; table19=16hA920; table110=16h9120; table111=16h8120; table112=16h8222; table113=16h8222; table114=16h8422; table115=16h881E; end end always(posedge mainclk)count=count+1;assign clk_24=count3;always(posedge clk_24 or negedge rst)if(!rst)beginstate=0;c

16、nt_595=0;cnt_164=0;temp=16h0000;endelsecase(state)0: begin AB=0; CLK=0;state=state+1;end1: begin CLK=1; state=state+1; end2: begin CLK=0; RCK=0;state=state+1;end3: begin temp=table1cnt_164;state=state+1;end4: begin SRCK=0; DATA=tempcnt_595;state=state+1; end5: begin SRCK=1; state=state+1; end6: if(c

17、nt_595 = 15) begin state=7;cnt_595=0;end else begin state=4; cnt_595=cnt_595+1; end7: begin AB=1;state=state+1;end8: begin RCK=1; state=state+1;end9: begin CLK=1; state=state+1; end10:/*if(delay_1641000) begin delay_164=delay_164+1; end else begin delay_164=0;state=state+1;end*/ begin state=state+1;

18、end11: if(cnt_164 = 15) begin state=0;cnt_164=0;end else begin state=2; cnt_164=cnt_164+1; enddefault:begin state=0;cnt_164=0;cnt_595=0;end endcaseendmodule6、实验遇到的问题及解决办法（余留问题、体会等）代码下载后总是不能正确显示，以为代码有问题，最后更换点阵屏后正确了。顶层实体名称和工程名必须一样；顶层实体为bdf文件。verilog文件（.v）都为子模块，不能与工程名或顶层实体名一样。所有verilog文件（.v）里面的模块名必须和这个verilog文件（.v）的文件名一样.