八位16进制八位10进制频率计设计.docx

1、八位16进制八位10进制频率计设计EDA综合实习报告一李爱 20111154006 电子科学与技术2011级1. 数字频率计的设计（1）8位16进制频率计主程序：LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY MAIN IS PORT (A,clk1,CLK: IN STD_LOGIC; O:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); P: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END;ARCHITECTURE HEAD OF

2、 MAIN IS COMPONENT CEPIN PORT (CLK1:IN STD_LOGIC; CNT: OUT STD_LOGIC; RST:OUT STD_LOGIC; LOAD:OUT STD_LOGIC); END COMPONENT; COMPONENT JISHU PORT (CLR:IN STD_LOGIC; EN:IN STD_LOGIC; FIN:IN STD_LOGIC; COUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT SUOCUN PORT( LK :IN STD_LOGIC; DI

3、N:IN STD_LOGIC_VECTOR (31 DOWNTO 0); QDOUT: OUT STD_LOGIC_VECTOR (31 DOWNTO 0); END COMPONENT; COMPONENT XIANSHI PORT (clk: in std_logic; Q:IN STD_LOGIC_VECTOR(31 DOWNTO 0); T:buffer STD_LOGIC_VECTOR(2 DOWNTO 0); Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); END COMPONENT; SIGNAL NET1,NET2,NET3:STD_LOGIC; SIG

4、NAL NET4,NET5 :STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN U1:CEPIN PORT MAP (CLK1=CLK,CNT=NET1,RST=NET2,LOAD=NET3); U2:JISHU PORT MAP (CLR=NET2,EN=NET1,FIN=A,COUT=NET4); U3:SUOCUN PORT MAP (LK=NET3,DIN=NET4,QDOUT=NET5); U4:XIANSHI PORT MAP (clk=clk1,Q=NET5,Y=P,T=O);END HEAD;测频LIBRARY IEEE; USE IEEE.STD_LO

5、GIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cepin IS PORT (CLK1:IN STD_LOGIC; CNT: OUT STD_LOGIC; RST:OUT STD_LOGIC; LOAD:OUT STD_LOGIC); END ; ARCHITECTURE one OF cepin IS SIGNAL M: STD_LOGIC; BEGIN PROCESS (CLK1) BEGIN IF CLK1 EVENT AND CLK1=1 THEN M= NOT M;END IF; END PROCESS; PROCESS (

6、CLK1,M) BEGIN IF CLK1=0 AND M=0 THEN RST=1; ELSE RST =0; END IF; END PROCESS; LOAD = NOT M; CNT =M; END one;计数LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JISHU IS PORT (CLR:IN STD_LOGIC; EN:IN STD_LOGIC; FIN:IN STD_LOGIC; COUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)

7、);END ; ARCHITECTURE two OF JISHU IS SIGNAL Q: STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN PROCESS (CLR,EN,FIN) BEGIN IF CLR=1 THEN Q 0); ELSIF FIN EVENT AND FIN=1 THEN IF EN=1 THEN Q = Q+1; END IF; END IF; END PROCESS; COUT =Q; END two;锁存LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGN

8、ED.ALL; ENTITY SUOCUN IS PORT( LK :IN STD_LOGIC; DIN:IN STD_LOGIC_VECTOR (31 DOWNTO 0); qDOUT: OUT STD_LOGIC_VECTOR (31 DOWNTO 0); END ; ARCHITECTURE three OF SUOCUN IS BEGIN PROCESS (LK,DIN) BEGIN IF LK EVENT AND LK=1 THEN qDOUT T=000;YT=000;YT=000;YT=000;YT=000;YT=000;YT=000;YT=000;YT=000;YT=000;Y

9、T=000;YT=000;YT=000;YT=000;YT=000;YT=000;Y NULL; END CASE; elsif Q1=0010 then CASE Q(7 downto 4) IS WHEN 0000=T=001;YT=001;YT=001;YT=001;YT=001;YT=001;YT=001;YT=001;YT=001;YT=001;YT=001;YT=001;YT=001;YT=001;YT=001;YT=001;Y NULL; END CASE; elsif Q1=0011then CASE Q(11 downto 8) IS WHEN 0000=T=010;YT=0

10、10;YT=010;YT=010;YT=010;YT=010;YT=010;YT=010;YT=010;YT=010;YT=010;YT=010;YT=010;YT=010;YT=010;YT=010;Y NULL; END CASE; elsif Q1=0100 then CASE Q(15 downto 12) IS WHEN 0000=T=011;YT=011;YT=011;YT=011;YT=011;YT=011;YT=011;YT=011;YT=011;YT=011;YT=011;YT=011;YT=011;YT=011;YT=011;YT=011;YNULL; END CASE;

11、elsif Q1=0101 then CASE Q(19 downto 16) IS WHEN 0000=T=100;YT=100;YT=100;YT=100;YT=100;YT=100;YT=100;YT=100;YT=100;YT=100;YT=100;YT=100;YT=100;YT=100;YT=100;YT=100;Y NULL; END CASE; elsif Q1=0110 then CASE Q(23 downto 20) IS WHEN 0000=T=101;YT=101;YT=101;YT=101;YT=101;YT=101;YT=101;YT=101;YT=101;YT=

12、101;YT=101;YT=101;YT=101;YT=101;YT=101;YT=101;Y NULL; END CASE; elsif Q1=0111 then CASE Q(27 downto 24) IS WHEN 0000=T=110;YT=110;YT=110;YT=110;YT=110;YT=110;YT=110;YT=110;YT=110;YT=110;YT=110;YT=110;YT=110;YT=110;YT=110;YT=110;Y NULL; END CASE; elsif Q1=1000 then CASE Q(31 downto 28) IS WHEN 0000=T

13、=111;YT=111;YT=111;YT=111;YT=111;YT=111;YT=111;YT=111;YT=111;YT=111;YT=111;YT=111;YT=111;YT=111;YT=111;YT=111;Y NULL; END CASE;end if; END PROCESS; END four;引脚：A：测频端口CLK：1Hz输入频率CLK1：2048Hz的刷新频率O：三八译码器选择端口P：数码管显示（2）8位10进制频率计主程序 ：LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MAIN IS PORT (CLK1,FSI

14、N:IN STD_LOGIC; CLK:IN STD_LOGIC; E:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); DOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); END ; ARCHITECTURE HEAD OF MAIN IS COMPONENT JISHU PORT(CLK,RST,EN:IN STD_LOGIC; CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT :OUT STD_LOGIC); END COMPONENT; COMPONENT CEPINPORT (CLK:IN STD_LOGI

15、C; TSTEN:OUT STD_LOGIC; CLR_CNT:OUT STD_LOGIC; LOAD:OUT STD_LOGIC); END COMPONENT; COMPONENT SUOCUN PORT(LOAD:IN STD_LOGIC; DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT :OUT STD_LOGIC_VECTOR(31 DOWNTO 0); END COMPONENT; COMPONENT XIANSHIPORT (clk: in std_logic; Q:IN STD_LOGIC_VECTOR(31 DOWNTO 0); T:buffer STD_LOGIC_VECTOR(2 DOWNTO 0); Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); END COMPONENT; SIGNAL TSTEN:STD_LOGIC; SIGNAL CLR_CNT:STD_LOGIC; SIGNAL LOAD:STD_LOGIC; SIGNAL C1:STD_LOGIC; SIGNAL C2:STD_LOGIC; SIGNAL C3:STD_LOGIC; SIGNAL C4:ST