tq2440测试代码.docx

1、tq2440测试代码2440INIT.S;=; NAME: 2440INIT.S; DESC: C start up codes; Configure memory, ISR ,stacks; Initialize C-variables;= GET option.inc GET memcfg.inc GET 2440addr.incBIT_SELFREFRESH EQU (1 mrc p15,0,r0,c1,c0,0 DCD 0xe3800080 ;0xe3800080 = orr r0,r0,#0x80; /Big-endian DCD 0xee010f10 ;0xee010f10 = m

2、cr p15,0,r0,c1,c0,0 ENTRY_BUS_WIDTH=16 DCD 0x0f10ee11 DCD 0x0080e380 DCD 0x0f10ee01 ENTRY_BUS_WIDTH=8 DCD 0x100f11ee DCD 0x800080e3 DCD 0x100f01ee DCD 0xffffffff ;swinv 0xffffff is similar with NOP and run well in both endian mode. DCD 0xffffffff DCD 0xffffffff DCD 0xffffffff DCD 0xffffffff b ResetH

3、andler HandlerFIQ HANDLER HandleFIQHandlerIRQ HANDLER HandleIRQHandlerUndef HANDLER HandleUndefHandlerSWI HANDLER HandleSWIHandlerDabort HANDLER HandleDabortHandlerPabort HANDLER HandlePabortIsrIRQ sub sp,sp,#4 ;reserved for PC stmfd sp!,r8-r9 ldr r9,=INTOFFSET ldr r9,r9 ldr r8,=HandleEINT0 add r8,r

4、8,r9,lsl #2 ldr r8,r8 str r8,sp,#8 ldmfd sp!,r8-r9,pc LTORG;=; ENTRY;=ResetHandler ldr r0,=WTCON ;watch dog disable ldr r1,=0x0 str r1,r0 ldr r0,=INTMSK ldr r1,=0xffffffff ;all interrupt disable str r1,r0 ldr r0,=INTSUBMSK ldr r1,=0x7fff ;all sub interrupt disable str r1,r0 FALSE ; GPBDAT = (rGPFDAT

5、 & (0xf4) | (data & 0xf)1 ; means Fclk:Hclk is not 1:1. mrc p15,0,r0,c1,c0,0 orr r0,r0,#0xc0000000;R1_nF:OR:R1_iA mcr p15,0,r0,c1,c0,0 | mrc p15,0,r0,c1,c0,0 bic r0,r0,#0xc0000000;R1_iA:OR:R1_nF mcr p15,0,r0,c1,c0,0 ;Configure UPLL ldr r0,=UPLLCON ldr r1,=(U_MDIV12)+(U_PDIV4)+U_SDIV) ;Fin = 12.0MHz,

6、 UCLK = 48MHz str r1,r0 nop ; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed. nop nop nop nop nop nop ;Configure MPLL ldr r0,=MPLLCON ldr r1,=(M_MDIV12)+(M_PDIV4)+M_SDIV) ;Fin = 12.0MHz, FCLK = 400MHz str r1,r0 ;Check if the boot is caused by

7、the wake-up from SLEEP mode. ldr r1,=GSTATUS2 ldr r0,r1 tst r0,#0x2 ;In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler. bne WAKEUP_SLEEP EXPORT StartPointAfterSleepWakeUpStartPointAfterSleepWakeUp ;Set memory control registers adrl r0,SMRDATA ldr r1,=BWSCON ;BWSCON Address add r2, r

8、0, #52 ;End address of SMRDATA0 ldr r3, r0, #4 str r3, r1, #4 cmp r2, r0 bne %B0; When EINT0 is pressed, Clear SDRAM ; check if EIN0 button is pressed ldr r0,=GPFCON ldr r1,=0x0 str r1,r0 ldr r0,=GPFUP ldr r1,=0xff str r1,r0 ldr r1,=GPFDAT ldr r0,r1 bic r0,r0,#(0x1e1 ; means Fclk:Hclk is not 1:1.; b

9、l MMU_SetAsyncBusMode; |; bl MMU_SetFastBusMode ; default value.; ;= ; Setup IRQ handler ldr r0,=HandleIRQ ;This routine is needed ldr r1,=IsrIRQ ;if there is not subs pc,lr,#4 at 0x18, 0x1c str r1,r0 :LNOT:THUMBCODE bl Main ;Do not use main() because . b . THUMBCODE ;for start-up code for Thumb mod

10、e orr lr,pc,#1 bx lr CODE16 bl Main ;Do not use main() because . b . CODE32 ;function initializing stacksInitStacks ;Do not use DRAM,such as stmfd,ldmfd. ;SVCstack is initialized before ;Under toolkit ver 2.5, msr cpsr,r1 can be used instead of msr cpsr_cxsf,r1 mrs r0,cpsr bic r0,r0,#MODEMASK orr r1

11、,r0,#UNDEFMODE|NOINT msr cpsr_cxsf,r1 ;UndefMode ldr sp,=UndefStack ; UndefStack=0x33FF_5C00 orr r1,r0,#ABORTMODE|NOINT msr cpsr_cxsf,r1 ;AbortMode ldr sp,=AbortStack ; AbortStack=0x33FF_6000 orr r1,r0,#IRQMODE|NOINT msr cpsr_cxsf,r1 ;IRQMode ldr sp,=IRQStack ; IRQStack=0x33FF_7000 orr r1,r0,#FIQMOD

12、E|NOINT msr cpsr_cxsf,r1 ;FIQMode ldr sp,=FIQStack ; FIQStack=0x33FF_8000 bic r0,r0,#MODEMASK|NOINT orr r1,r0,#SVCMODE msr cpsr_cxsf,r1 ;SVCMode ldr sp,=SVCStack ; SVCStack=0x33FF_5800 ;USER mode has not be initialized. mov pc,lr ;The LR register will not be valid if the current mode is not SVC mode

13、. LTORGSMRDATA DATA; Memory configuration should be optimized for best performance; The following parameter is not optimized.; Memory access cycle parameter strategy; 1) The memory settings is safe parameters even at HCLK=75Mhz.; 2) SDRAM refresh period is for HCLK=75Mhz. DCD (0+(B1_BWSCON4)+(B2_BWSCON8)+(B3_BWSCON12)+(B4_BWSCON16)+(B5_BWSCON20)+(B6_BWSCON24)+(B7_BWSCON28) DCD (B0_Tacs13)+(B0_Tcos11)+(B0_Tacc8)+(B0_Tcoh6)+(B0_Tah4)+(B0_Tacp2)+(B0_PMC) ;GCS0 DCD (B1_Tacs13)+(B1_Tcos11)+(B1_Tacc8)+(B1_Tcoh6)+(B1_Tah4)+(B1_Tacp2)+(B1_PMC) ;GCS1 DCD (B2_Tacs13)+(B2_Tcos11)+(B2_T