1、组合逻辑电路设计案例二输入与门程序1:出处:4.1.1 例4-1知识点:注意代入语句使用时与实际电路工作情况保持一致,延时是必须要考虑的因素。ENTITY and2 ISPORT (a,b:IN BIT; c:OUT BIT);END ENTITY and2; ARCHITECTURE and2_behav OF and2 ISBEGIN c=a AND b AFTER 5ns;END ARCHITECTURE and2_behav;程序2:ENTITY and2 ISGENERIC (rise,fall:TIME); PORT (a,b: IN BIT; c: OUT BIT)END ENT
2、ITY and2;ARCHITECTURE behav OF and2 ISSIGNAL internal:BIT; BEGIN internal=a AND b;出处:4.1.4 例4-4知识点:GENERIC语句常用于不同层次之间点的信息传递,该例中使用GENERIC语句分别对信号的上升时间和下降时间进行了定义。cyyyyy=X; END CASE; END PROCESS t1; END ARCHITECTURE nand2_2;三态门电路程序1:出处:7.1.4 例7-15知识点:利用IF语句的多选择分支功能描述三态门,注意输入、输出间的控制关系。LIBRARY IEEE;USE IE
3、EE.STD_LOGIC_1164.ALL;ENTITY tri_gate ISPORT (din, en:IN STD_LOGIC; dout:OUT STD_LOGIC);END ENTITY tri_gate;ARCHITECTURE zas OF tri_gate ISBEGINtri_gate1:PROCESS (din, en)IS BEGINIF (en=1) THEN dout=din; ELSE dout=Z; END IF; END PROCESS;END ARCHITECTURE zas;程序2:出处:7.1.4 例7-16知识点:使用卫式BLOCK结构描述,注意条件的设
4、立。ARCHITECTURE blk OF tri_gate ISBEGINtri_gate2:BLOCK (en=1) BEGIN dout=GUARDED din;END BLOCK;END ARCHITECTURE blk;八位单向总线缓冲器程序1:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY tri_buf8 ISPORT (din: IN STD_LOGIC_VECTOR (7 DOWNTO 0) ; dout: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); en:IN STD_LOGIC);END ENTIT
5、Y tri_buf8;ARCHITECTURE zas OF tri_buf8 ISBEGIN出处:7.1.4 例7-15知识点:采用进程结构,使用IF语句描述器件逻辑功能。tri_buff: PROCESS (en, din)IS BEGIN IF (en=1 ) THEN dout=din; ELSE dout=ZZZZZZZZ; END IFEND PROCESS;END ARCHITECTURE zas;双向总线缓冲器程序1:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY tri_bigate ISPORT (a, b:INOUT STD
6、_LOGIC_VECTOR (7 DOWNTO 0); en:IN STD_LOGIC; dr:IN STD_LOGIC);END ENTITY tri_bigate;ARCHITECTURE rtl OF tri_bigate出处:7.1.4 例7-23知识点:使用两个进程语句分别对两个方向上的数据传输进行描述。SIGNAL aout, bout:STD_LOGIC_VECTOR (7 DOWNTO 0);BEGIN PROCESS (a, dr, en)IS BEGIN IF (en=0) AND (dr=1) THEN bout=a; ELSE bout=ZZZZZZZZ; END IF
7、; b=bout;END PROCESS; PROCESS (b, dr, en)IS BEGIN IF (en=0) AND (dr=0) THEN aout=b; ELSE aout=ZZZZZZZZ; END IF; a=aout;END PROCESS;END ARCHITECTURE rtl;位矢量/整数转换器程序1:出处:2.2.3 例2-7知识点:构造体采用子程序语句结构的过程语句(PROCEDURE),掌握语句的书写格式即使用方法。PROCEDURE vector_to_int (z:IN STD_LOGIC_VECTOR; x_f1ag: OUT BOOLEAN; q: IN
8、OUT INTEGER) IS BEGIN q:=0; x_f1ag:=FALSE; FOR i IN zRANGE LOOP q:=q*2;IF(z(i)=1) THEN q:=q+1; ELSIF(z(i)/=0) THEN x_f1ag:=TRUE; END IF END LOOP; END PROCEDURE vector_to_int;标准逻辑矢量/整数转换器程序1:出处:3.2.4 例3-1知识点:程序中使用了转换函数,掌握VHDL语言中常用的转换函数的使用方法和所在的包集合。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD
9、_LOGIC_UNSIGNED.ALL;ENTITY add5 IS PORT (num:IN STD_LOGIC_VECTOR (2 DOWNTO 0); );END ENTITY add5;ARCHITECTURE rtl OF add5 IS SIGNAL in_num:INTEGER RANGE 0 TO 5; BEGIN in_num=CONV_INTEGER (num); END ARCHITECTURE rtl;并置运算器程序1:出处:3.3.4 知识点:注意位并置符的使用方法和使用时的注意事项。tmp_b=b AND (en&en&en&en);y=a & tmp_b;八位奇偶
10、校验电路程序1:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY parity_check ISPORT(a: IN STD_LOGIC_VECTOR(7 DOWNTO 0); y: OUT STD_LOGIC);END ENTITY parity_check;ARCHITECTURE rtl OF parity_check ISBEGIN PROCESS(a) IS出处:5.1.7 例5-13知识点:注意LOOP语句的书写格式及使用。VARIABLE tmp: STD_LOGIC; BEGIN tmp:=0; FOR i IN 0 TO 7 LO
11、OP tmp:=tmp XOR a(i); END LOOP; y=tmp; END PROCESS; END ARCHITECTURE rtl;程序2:LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY parity_check ISPORT(a: IN STD_LOGIC_VECTOR(7 DOWNTO 0); y: OUT STD_LOGIC);END ENTITY parity_check;ARCHITECTURE behav OF parity_check ISBEGIN PROCESS(a) ISVARIABLE tmp: STD_LO
12、GIC; BEGIN tmp:= 0; i:=0; WHILE (i8) LOOP tmp:=tmp XOR a(i); i:=i+1; END LOOP; y=tmp; END PROCESS;END ARCHITECTURE behav;出处:5.1.7 例5-14知识点:使用带WHILE条件的LOOP语句描述八位奇偶校验电路的逻辑功能。加法器程序1:出处:7.1.3 例7-15知识点:采用COMPONENT语句和PORT MAP语句调用已定义原件半加器half_adder描述全加器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY full_
13、adder ISPORT (a, b, cin:IN STD_LOGIC; s, co:OUT STD_LOGIC);END ENTITY full_adder;ARCHITECTURE full1 OF full_adder ISCOMPONENT half_adder IS PORT (a, b:IN STD_LOGIC;s, co:OUT STD_LOGIC);END COMPONENT;SIGNAL u0_co, u0_s, u1_co:STD_LOGIC;BEGIN u0:half_adder PORT MAP (a, b, u0_s, u0_co); u1:half_adder P
14、ORT MAP (u0_s, cin, s, u1_co); co=u0_co OR u1_co;END ARCHITECTURE full1;半加器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY half_adder ISPORT (a, b:IN STD_LOGIC;s, co:OUT STD_LOGIC);END ENTITY half_adder;ARCHITECTURE half1 OF half_adder ISSIGNAL c, d:STD_LOGIC;BEGIN c=a OR b;d=a NAND b;co=NOT d;s=c A
15、ND d;END ARCHITECTURE half1;二选一选择器程序1:出处:1.2知识点:理解硬件描述语言能够比电原理图更有效的表示硬件电路的特性。ENTITY mux IS GENERIC(m:TIME: =1ns);PORT (d0,d1:IN BIT; sel:IN BIT; q:OUT BIT);END ENTITY mux; ARCHITECTURE connect OF mux IS BEGIN 出处:2.1知识点:作为一个完整的VHDL程序出现,掌握程序框架的结构;实体与构造体的书写格式;各项参数的含义。PROCESS(d0,d1,sel)ISVARIBLE temp1,t
16、emp2,temp3:BIT;BEGINtemp1:=d0 AND sel;temp2:=d1 AND (NOTsel);temp3:=temp1 OR temp2;q=temp3 AFTER m;END PROCESSEND ARCHITECTURE connect;程序2(与程序1的描述方式一致,但对原件逻辑功能的描述更简单):出处:2.1.2 例2-3知识点:构造体内部语句采用并行处理方式,即介于BEGIN与END之间的语句将会被同时执行。ENTITY mux IS PORT (d0,d1:IN BIT; sel:IN BIT; q:OUT BIT);END ENTITY mux; AR
17、CHITECTURE dataflow OF mux IS BEGIN q=(d0 AND sel)OR(NOT sel AND d1); END ARCHITECTURE dataflow;程序3:ENTITY mux ISPORT(d0,d1,sel: IN BIT; q: OUT BIT);END ENTITY mux;ARCHITECTURE connect OF mux ISSIGNAL tmp1,tmp2,tmp3: BIT;BEGIN cale:BLOCK出处:2.2.1 例2-4知识点:构造体采用BLOCK结构,掌握块语句结构的书写格式及使用方法。BEGIN tmp1=d0 A
18、ND sel; tmp2=d1 AND (NOT sel); tmp3=tmp1 OR tmp2; q=tmp3; END BLOCK cale;END ARCHITECTURE connect;程序4:出处:2.2.2 例2-6知识点:构造体采用进程语句结构,掌握进程(PROCESS)语句结构的书写格式及使用方法。ENTITY mux ISPORT(d0,d1,sel: IN BIT; q: OUT BIT);END ENTITY mux;ARCHITECTURE connect OF mux IS BEGIN cale: PROCESS(d0,d1,sel) IS VARIABLE tmp
19、1,tmp2,tmp3: BIT; BEGINtmp1:=d0 AND sel; tmp2:=d1 AND (NOT sel); tmp3:=tmp1 OR tmp2; q=tmp3 ; END PROCESS cale; END ARCHITECTURE connect;程序5:ENTITY mux2 ISPORT (d0,d1,sel:IN BIT; q:OUT BIT);END ENTITY mux2;ARCHITECTURE struct OF mux2 ISCOMPONENT and2 IS PORT (a,b:IN BIT; c:OUT BIT);END COMPONENT;出处:
20、4.3.1 例4-16知识点:二选一电路采用结构化的方式描述构造体,使用了COMPONENT语句和PORT MAP语句,属于最底层的描述方式,与实际电路最贴近。COMPONENT or2 IS PORT (a,b:IN BIT; c:OUT BIT);END COMPONENT;COMPONENT inv IS PORT (a:IN BIT; c:OUT BIT);END COMPONENT;SIGNAL aa,ab,nsel:BIT;BEGIN u1:inv PORT MAP (sel,nsel);u2:and2 PORT MAP (nsel,d1,ab); u3:and2 PORT MAP
21、 (d0,sel,aa); u4:or2 PORT MAP (aa,ab,q);END ARCHITECTURE struct;程序6:出处:5.1.5 例5-7知识点:利用IF语句的二选择控制功能对二选一电路的逻辑控制进行描述。ARCHITECTURE rtl OF mux2 ISBEGINPROCESS (a, b, sel) ISBEGINIF (sel=1) THENc=a;ELSEc=b;END IF; END PROCESS; END ARCHITECTURE rtl;四选一选择器程序1:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IE
22、EE.STD_LOGIC_UNSIGNED.ALL;ENTITY mux4 IS PORT (i0,i1,i2,i3,a,b:IN STD_LOGIC; q:OUT STD_LOGIC);END ENTITY mux4;ARCHITECTURE behav OF mux4 ISSIGNAL sel:INTEGER;出处:5.2.4 例5-18知识点:注意选择信号代入语句的使用。条件并行执行,不具有优先级。出处:4.1.1 例4-2知识点:注意条件代入语句的使用。BEGIN WITH sel SELECT q=i0 AFTER 10ns WHEN 0, i1 AFTER 10ns WHEN 1,
23、 i2 AFTER 10ns WHEN 2, i3 AFTER 10ns WHEN 3, X AFTER 10ns WHEN OTHERS; sel=0 WHEN a=0 AND b=0 ELSE 1 WHEN a=1 AND b=0 ELSE 2 WHEN a=0 AND b=1 ELSE3 WHEN a=1 AND b=1 ELSE 4;END ARCHITECTURE behav;程序2:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGEND.ALL;ENTITY mux4 ISPORT (input:IN
24、 STD_LOGIC_VECTOR (3 DOWNTO 0); sel:IN STD_LOGIC_VECTOR (1 DOWNTO 0); y:OUT STD_LOGIC);出处:4.2.1 例4-6知识点:采用RTL描述方式描述四选一电路,注意构造体的逻辑功能描述的方法,与上例进行比较。END ENTITY mux4;ARCHITECTURE rtl OF mux4 ISBEGINy=input(0) WHEN sel=00 ELSE input(1) WHEN sel=01 ELSE input(2) WHEN sel=10 ELSE input(3);END ARCHITECTURE r
25、tl;程序3:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux4 ISPORT(input: IN STD_LOGIC_VECTOR (3 DOWNTO 0); sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0); y: OUT STD_LOGIC);END ENTITY mux4;ARCHITECTURE rtl OF mux4 ISBEGIN出处:5.1.5 例5-8知识点:利用IF语句的多选择控制功能对四选一电路的逻辑功能进行描述;选择条件顺序执行,具有优先级。注意语句自身为顺序语句。PROCESS(input
26、, sel) IS BEGIN IF(sel=00) THEN y=input(0); ELSIF(sel=01) THEN y=input(1); ELSIF(sel=10) THEN y=input(2); ELSE y=input(3);END IF; END PROCESS; END ARCHITECTURE rtl;程序4:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux4 ISPORT(a,b,i0,i1,i2,i3: IN STD_LOGIC; q: OUT STD_LOGIC);END ENTITY mux4;ARCHITECTURE mux4_behave OF mux4 ISSIGNAL sel: INTEGER RANGE 0 TO 3;BEG
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